diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2011-01-14 20:39:19 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-14 20:39:19 +0100 |
| commit | 69d1fc221a0bcd6a9a17e79ab933ab7525f15973 (patch) | |
| tree | c0dae88cf8c7a52b1047588643af63250b4ed13c /target-arm | |
| parent | 5df8bac1d3ea43b7f55ffab07cbc6d81a37d82ab (diff) | |
| download | qemu-69d1fc221a0bcd6a9a17e79ab933ab7525f15973.tar.gz qemu-69d1fc221a0bcd6a9a17e79ab933ab7525f15973.tar.bz2 qemu-69d1fc221a0bcd6a9a17e79ab933ab7525f15973.zip | |
target-arm: Translate with VFP len/stride from TB flags, not CPUState
When translating, the VFP vector length and stride for this TB are encoded
in the TB flags; the CPUState copies may be different and must not be used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index f8e3616564..e15d10b251 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -60,6 +60,8 @@ typedef struct DisasContext { int user; #endif int vfp_enabled; + int vec_len; + int vec_stride; } DisasContext; #if defined(CONFIG_USER_ONLY) @@ -2895,7 +2897,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) rm = VFP_SREG_M(insn); } - veclen = env->vfp.vec_len; + veclen = s->vec_len; if (op == 15 && rn > 3) veclen = 0; @@ -2916,9 +2918,9 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) veclen = 0; } else { if (dp) - delta_d = (env->vfp.vec_stride >> 1) + 1; + delta_d = (s->vec_stride >> 1) + 1; else - delta_d = env->vfp.vec_stride + 1; + delta_d = s->vec_stride + 1; if ((rm & bank_mask) == 0) { /* mixed scalar/vector */ @@ -9104,6 +9106,8 @@ static inline void gen_intermediate_code_internal(CPUState *env, } #endif dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); + dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); + dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); cpu_F0d = tcg_temp_new_i64(); |