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| author | Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> | 2011-04-19 18:56:45 +0400 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-04-20 12:59:15 +0200 |
| commit | 5bc95aa2461f3b9f70ecbb2a9ec22f939fc33d6d (patch) | |
| tree | bed2759f973d982286eadf7f00c5100600ba0bec /target-arm | |
| parent | 618ba8e6a1313df6a8366ac8ffee47e3f885ac90 (diff) | |
| download | qemu-5bc95aa2461f3b9f70ecbb2a9ec22f939fc33d6d.tar.gz qemu-5bc95aa2461f3b9f70ecbb2a9ec22f939fc33d6d.tar.bz2 qemu-5bc95aa2461f3b9f70ecbb2a9ec22f939fc33d6d.zip | |
Implement basic part of SA-1110/SA-1100
Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation.
Implemented:
- IRQs
- GPIO
- PPC
- RTC
- UARTs (no IrDA/etc.)
- OST reused from pxa25x
Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the
hw/strongarm.c
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu.h | 3 | ||||
| -rw-r--r-- | target-arm/helper.c | 9 |
2 files changed, 12 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e247a7ade0..d5af64465f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -363,6 +363,7 @@ enum arm_features { ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ ARM_FEATURE_V4T, ARM_FEATURE_V5, + ARM_FEATURE_STRONGARM, }; static inline int arm_feature(CPUARMState *env, int feature) @@ -393,6 +394,8 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_ARM946 0x41059461 #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 +#define ARM_CPUID_SA1100 0x4401A11B +#define ARM_CPUID_SA1110 0x6901B119 #define ARM_CPUID_PXA250 0x69052100 #define ARM_CPUID_PXA255 0x69052d00 #define ARM_CPUID_PXA260 0x69052903 diff --git a/target-arm/helper.c b/target-arm/helper.c index 12127dee74..bf843353e0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -214,6 +214,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0xd172172; env->cp15.c1_sys = 0x00000078; break; + case ARM_CPUID_SA1100: + case ARM_CPUID_SA1110: + set_feature(env, ARM_FEATURE_STRONGARM); + env->cp15.c1_sys = 0x00000070; + break; default: cpu_abort(env, "Bad CPU ID: %x\n", id); break; @@ -378,6 +383,8 @@ static const struct arm_cpu_t arm_cpu_names[] = { { ARM_CPUID_CORTEXA9, "cortex-a9"}, { ARM_CPUID_TI925T, "ti925t" }, { ARM_CPUID_PXA250, "pxa250" }, + { ARM_CPUID_SA1100, "sa1100" }, + { ARM_CPUID_SA1110, "sa1110" }, { ARM_CPUID_PXA255, "pxa255" }, { ARM_CPUID_PXA260, "pxa260" }, { ARM_CPUID_PXA261, "pxa261" }, @@ -1553,6 +1560,8 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) case 9: if (arm_feature(env, ARM_FEATURE_OMAPCP)) break; + if (arm_feature(env, ARM_FEATURE_STRONGARM)) + break; /* Ignore ReadBuffer access */ switch (crm) { case 0: /* Cache lockdown. */ switch (op1) { |