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| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2014-09-29 18:48:51 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-09-29 18:48:51 +0100 |
| commit | 041c96666d0480380e50fe66fc66cc35bddcf741 (patch) | |
| tree | a98a0c8c5daab4becd0a06adc2ae2191bb076af0 /target-arm | |
| parent | e0d6e6a5e799c91b74e157ca2cb7f4d2dbc0d56b (diff) | |
| download | qemu-041c96666d0480380e50fe66fc66cc35bddcf741.tar.gz qemu-041c96666d0480380e50fe66fc66cc35bddcf741.tar.bz2 qemu-041c96666d0480380e50fe66fc66cc35bddcf741.zip | |
target-arm: Add IRQ and FIQ routing to EL2 and 3
Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1411718914-6608-11-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu.h | 10 | ||||
| -rw-r--r-- | target-arm/helper.c | 17 |
2 files changed, 27 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d104a7d704..11ba9d6c02 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1180,6 +1180,10 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) CPUARMState *env = cs->env_ptr; unsigned int cur_el = arm_current_pl(env); unsigned int target_el = arm_excp_target_el(cs, excp_idx); + /* FIXME: Use actual secure state. */ + bool secure = false; + /* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */ + bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2; /* Don't take exceptions if they target a lower EL. */ if (cur_el > target_el) { @@ -1188,8 +1192,14 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) switch (excp_idx) { case EXCP_FIQ: + if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) { + return true; + } return !(env->daif & PSTATE_F); case EXCP_IRQ: + if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) { + return true; + } return !(env->daif & PSTATE_I) && (!IS_M(env) || env->regs[15] < 0xfffffff0); default: diff --git a/target-arm/helper.c b/target-arm/helper.c index af2d2e670a..6135594252 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3773,6 +3773,8 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) CPUARMState *env = &cpu->env; unsigned int cur_el = arm_current_pl(env); unsigned int target_el; + /* FIXME: Use actual secure state. */ + bool secure = false; if (!env->aarch64) { /* TODO: Add EL2 and 3 exception handling for AArch32. */ @@ -3787,6 +3789,21 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) case EXCP_SMC: target_el = 3; break; + case EXCP_FIQ: + case EXCP_IRQ: + { + const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO; + const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ; + + target_el = 1; + if (!secure && (env->cp15.hcr_el2 & hcr_mask)) { + target_el = 2; + } + if (env->cp15.scr_el3 & scr_mask) { + target_el = 3; + } + break; + } default: target_el = MAX(cur_el, 1); break; |