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authorPeter Maydell <peter.maydell@linaro.org>2016-06-06 16:59:28 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-06-06 16:59:28 +0100
commit78f1edb19fe11fa0c5d0bf484db59a384f455d3c (patch)
tree297a7053371c0396551fa95caa89370ab39f34a1 /target-arm
parent04ce861ea545477425ad9e045eec3f61c8a27df9 (diff)
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target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64()
Remove some incorrect code from arm_cpu_do_interrupt_aarch64() which attempts to set the IL bit in the syndrome register based on the value of env->thumb. This is wrong in several ways: * IL doesn't indicate Thumb-vs-ARM, it indicates instruction length (which may be 16 or 32 for Thumb and is always 32 for ARM) * not every syndrome format uses IL like this -- for some IL is always set, and for some it is always clear * the code is changing esr_el[new_el] even for interrupt entry, which is not supposed to modify ESR_ELx at all Delete the code, and instead rely on the syndrome value in env->exception.syndrome having already been set up with the correct value of IL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1463487258-27468-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/helper.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9a6ff2e2ba..86a094d14a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6365,9 +6365,6 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
env->elr_el[new_el] = env->pc;
} else {
env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
- if (!env->thumb) {
- env->cp15.esr_el[new_el] |= 1 << 25;
- }
env->elr_el[new_el] = env->regs[15];
aarch64_sync_32_to_64(env);