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| author | Andreas Färber <andreas.faerber@web.de> | 2011-12-13 18:19:24 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2011-12-13 18:19:24 +0000 |
| commit | 10e87702745b89d56678edad9da9efb6fce4ea71 (patch) | |
| tree | e8774bedd8b869e506d7c380d7ae7fc300f84ab1 /target-arm | |
| parent | bbc5c5fa177156299eca4dd7fceb04cb42035c14 (diff) | |
| download | qemu-10e87702745b89d56678edad9da9efb6fce4ea71.tar.gz qemu-10e87702745b89d56678edad9da9efb6fce4ea71.tar.bz2 qemu-10e87702745b89d56678edad9da9efb6fce4ea71.zip | |
target-arm: Infer AUXCR feature from ARMv6
V6 && !M => AUXCR
Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/helper.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 1108156530..0a7f7458fa 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -84,7 +84,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) */ set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); /* These ID register values are correct for 1136 but may be wrong * for 1136_r2 (in particular r0p2 does not actually implement most * of the ID registers). @@ -100,7 +99,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_ARM1176: set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; @@ -113,7 +111,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_ARM11MPCORE: set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_VAPA); env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; @@ -124,7 +121,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_CORTEXA8: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); @@ -144,7 +140,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_CORTEXA9: set_feature(env, ARM_FEATURE_V7); - set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); @@ -244,6 +239,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); + if (!arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_AUXCR); + } } if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); |