diff options
| author | Andrew Baumann <Andrew.Baumann@microsoft.com> | 2015-12-17 13:37:13 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-12-17 13:37:13 +0000 |
| commit | 30901475b91ef1f46304404ab4bfe89097f61b96 (patch) | |
| tree | b84b67f2ea28863d0d1c13e2d5060d81efd733bb /target-arm/translate.c | |
| parent | 580106df5ff1a86df317c8a8080e48e1694d785e (diff) | |
| download | qemu-30901475b91ef1f46304404ab4bfe89097f61b96.tar.gz qemu-30901475b91ef1f46304404ab4bfe89097f61b96.tar.bz2 qemu-30901475b91ef1f46304404ab4bfe89097f61b96.zip | |
target-arm: raise exception on misaligned LDREX operands
Qemu does not generally perform alignment checks. However, the ARM ARM
requires implementation of alignment exceptions for a number of cases
including LDREX, and Windows-on-ARM relies on this.
This change adds plumbing to enable alignment checks on loads using
MO_ALIGN, a do_unaligned_access hook to raise the exception (data
abort), and uses the new aligned loads in LDREX (for all but
single-byte loads).
Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Message-id: 1449167808-5656-1-git-send-email-Andrew.Baumann@microsoft.com
[PMM: set WnR bits in syndrome and FSR as appropriate]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 5d22879755..12dbfacaf2 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -926,13 +926,13 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) #define DO_GEN_LD(SUFF, OPC) \ static inline void gen_aa32_ld##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \ { \ - tcg_gen_qemu_ld_i32(val, addr, index, OPC); \ + tcg_gen_qemu_ld_i32(val, addr, index, (OPC)); \ } #define DO_GEN_ST(SUFF, OPC) \ static inline void gen_aa32_st##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \ { \ - tcg_gen_qemu_st_i32(val, addr, index, OPC); \ + tcg_gen_qemu_st_i32(val, addr, index, (OPC)); \ } static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index) @@ -988,6 +988,9 @@ DO_GEN_LD(8u, MO_UB) DO_GEN_LD(16s, MO_TESW) DO_GEN_LD(16u, MO_TEUW) DO_GEN_LD(32u, MO_TEUL) +/* 'a' variants include an alignment check */ +DO_GEN_LD(16ua, MO_TEUW | MO_ALIGN) +DO_GEN_LD(32ua, MO_TEUL | MO_ALIGN) DO_GEN_ST(8, MO_UB) DO_GEN_ST(16, MO_TEUW) DO_GEN_ST(32, MO_TEUL) @@ -7435,11 +7438,11 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, gen_aa32_ld8u(tmp, addr, get_mem_index(s)); break; case 1: - gen_aa32_ld16u(tmp, addr, get_mem_index(s)); + gen_aa32_ld16ua(tmp, addr, get_mem_index(s)); break; case 2: case 3: - gen_aa32_ld32u(tmp, addr, get_mem_index(s)); + gen_aa32_ld32ua(tmp, addr, get_mem_index(s)); break; default: abort(); |