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| author | Fabian Aggeler <aggelerf@ethz.ch> | 2014-12-11 12:07:51 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-12-11 12:07:51 +0000 |
| commit | 88ca1c2d70523486a952065f3ed7b8fc823b5863 (patch) | |
| tree | 63cf24d393958c1127857da66b5de594fa2e5328 /target-arm/cpu.h | |
| parent | 0c17d68c1d3d6c35f37f5692042d2edb65c8bcc0 (diff) | |
| download | qemu-88ca1c2d70523486a952065f3ed7b8fc823b5863.tar.gz qemu-88ca1c2d70523486a952065f3ed7b8fc823b5863.tar.bz2 qemu-88ca1c2d70523486a952065f3ed7b8fc823b5863.zip | |
target-arm: make IFSR banked
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and
storage.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-20-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1906fc1fa6..e8bb057ffc 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -242,7 +242,15 @@ typedef struct CPUARMState { uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ uint64_t scr_el3; /* Secure configuration register. */ - uint32_t ifsr_el2; /* Fault status registers. */ + union { /* Fault status registers. */ + struct { + uint64_t ifsr_ns; + uint64_t ifsr_s; + }; + struct { + uint64_t ifsr32_el2; + }; + }; uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el[4]; /* Fault address registers. */ |