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| author | Jean-Christophe Dubois <jcd@tribudubois.net> | 2015-09-07 10:39:31 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-09-07 10:39:31 +0100 |
| commit | d4e26d106a1ea35a81176cb5398406b08316adc7 (patch) | |
| tree | 8b8d498010db1df7b8d3f7188c772348167cc7cf /include | |
| parent | 7f3986278b0bc214e83111ea55c8d12bac79c4fa (diff) | |
| download | qemu-d4e26d106a1ea35a81176cb5398406b08316adc7.tar.gz qemu-d4e26d106a1ea35a81176cb5398406b08316adc7.tar.bz2 qemu-d4e26d106a1ea35a81176cb5398406b08316adc7.zip | |
i.MX: Add i2C devices to i.MX31 SOC
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: fb20e6bf5cf946c4530b2cfb55c7e37f5a0fc051.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/arm/fsl-imx31.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h index 128006fd75..891166f2cc 100644 --- a/include/hw/arm/fsl-imx31.h +++ b/include/hw/arm/fsl-imx31.h @@ -31,6 +31,7 @@ #define FSL_IMX31_NUM_UARTS 2 #define FSL_IMX31_NUM_EPITS 2 +#define FSL_IMX31_NUM_I2CS 3 typedef struct FslIMX31State { /*< private >*/ @@ -43,6 +44,7 @@ typedef struct FslIMX31State { IMXSerialState uart[FSL_IMX31_NUM_UARTS]; IMXGPTState gpt; IMXEPITState epit[FSL_IMX31_NUM_EPITS]; + IMXI2CState i2c[FSL_IMX31_NUM_I2CS]; MemoryRegion secure_rom; MemoryRegion rom; MemoryRegion iram; @@ -57,10 +59,16 @@ typedef struct FslIMX31State { #define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000 #define FSL_IMX31_IRAM_ADDR 0x1FFFC000 #define FSL_IMX31_IRAM_SIZE 0x4000 +#define FSL_IMX31_I2C1_ADDR 0x43F80000 +#define FSL_IMX31_I2C1_SIZE 0x4000 +#define FSL_IMX31_I2C3_ADDR 0x43F84000 +#define FSL_IMX31_I2C3_SIZE 0x4000 #define FSL_IMX31_UART1_ADDR 0x43F90000 #define FSL_IMX31_UART1_SIZE 0x4000 #define FSL_IMX31_UART2_ADDR 0x43F94000 #define FSL_IMX31_UART2_SIZE 0x4000 +#define FSL_IMX31_I2C2_ADDR 0x43F98000 +#define FSL_IMX31_I2C2_SIZE 0x4000 #define FSL_IMX31_CCM_ADDR 0x53F80000 #define FSL_IMX31_CCM_SIZE 0x4000 #define FSL_IMX31_GPT_ADDR 0x53F90000 @@ -95,5 +103,8 @@ typedef struct FslIMX31State { #define FSL_IMX31_GPT_IRQ 29 #define FSL_IMX31_UART2_IRQ 32 #define FSL_IMX31_UART1_IRQ 45 +#define FSL_IMX31_I2C1_IRQ 10 +#define FSL_IMX31_I2C2_IRQ 4 +#define FSL_IMX31_I2C3_IRQ 3 #endif /* FSL_IMX31_H */ |