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| author | Roy Franz <roy.franz@linaro.org> | 2013-12-17 19:42:26 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-12-17 19:42:26 +0000 |
| commit | 1997b48527c38fe8cdbbb3df82ed79aa3ee88b83 (patch) | |
| tree | f39eb4c4a6806072d273d1f774724c0b87409b47 /hw | |
| parent | 4b6fedcac0f51157ef042cde80d5dc5d0c9ef8a4 (diff) | |
| download | qemu-1997b48527c38fe8cdbbb3df82ed79aa3ee88b83.tar.gz qemu-1997b48527c38fe8cdbbb3df82ed79aa3ee88b83.tar.bz2 qemu-1997b48527c38fe8cdbbb3df82ed79aa3ee88b83.zip | |
Add device-width property to pflash_cfi01
The width of the devices that make up the flash interface
is required to mask certain commands, in particular the
write length for buffered writes. This length will be presented
to each device on the interface by the program writing the flash,
and the flash emulation code needs to be able to determine
the length of the write as recieved by each flash device.
The device-width defaults to the bank width which should
maintain existing behavior for platforms that don't need
this change.
This change is required to support buffered writes on the
vexpress platform that has a 32 bit flash interface with 2
16 bit devices on it.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id: 1386279359-32286-3-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/block/pflash_cfi01.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index a0d7a161f4..a458ad62e9 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -40,6 +40,7 @@ #include "hw/block/flash.h" #include "block/block.h" #include "qemu/timer.h" +#include "qemu/bitops.h" #include "exec/address-spaces.h" #include "qemu/host-utils.h" #include "hw/sysbus.h" @@ -72,6 +73,7 @@ struct pflash_t { uint32_t nb_blocs; uint64_t sector_len; uint8_t bank_width; + uint8_t device_width; /* If 0, device width not specified. */ uint8_t be; uint8_t wcycle; /* if 0, the flash is read normally */ int ro; @@ -379,6 +381,14 @@ static void pflash_write(pflash_t *pfl, hwaddr offset, break; case 0xe8: + /* Mask writeblock size based on device width, or bank width if + * device width not specified. + */ + if (pfl->device_width) { + value = extract32(value, 0, pfl->device_width * 8); + } else { + value = extract32(value, 0, pfl->bank_width * 8); + } DPRINTF("%s: block write of %x bytes\n", __func__, value); pfl->counter = value; pfl->wcycle++; @@ -708,6 +718,7 @@ static Property pflash_cfi01_properties[] = { DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0), DEFINE_PROP_UINT8("width", struct pflash_t, bank_width, 0), + DEFINE_PROP_UINT8("device-width", struct pflash_t, device_width, 0), DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), |