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| author | Hervé Poussineau <hpoussin@reactos.org> | 2013-09-14 17:51:07 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2013-09-16 12:42:25 +0200 |
| commit | 0903c35ddeebde56772b39cf08e7a0bae2eb39eb (patch) | |
| tree | 5ec39b2a05a29f39f4062fea915547b01d5f8896 /hw | |
| parent | c7ac9f403af37439da0ce650b68bbcb13439768e (diff) | |
| download | qemu-0903c35ddeebde56772b39cf08e7a0bae2eb39eb.tar.gz qemu-0903c35ddeebde56772b39cf08e7a0bae2eb39eb.tar.bz2 qemu-0903c35ddeebde56772b39cf08e7a0bae2eb39eb.zip | |
lsi: ignore write accesses to CTEST0 registers
53C895A datasheet says that this register is read/write, and that the value
returned on read access is dependant of DMA FIFO state. However, nothing is
said for written value.
53C810A datasheet gives more insight about this register:
"This was a general purpose read/write register in previous SYM53C8XX
family chips. Although it is still a read/write register, Symbios reserves
the right to use these bits for future 53C8XX family enhancements."
This prevents going to the default case, which prints an error message.
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/scsi/lsi53c895a.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index 4314efe9f0..89d934b4be 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -1743,6 +1743,9 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) case 0x17: /* MBOX1 */ s->mbox1 = val; break; + case 0x18: /* CTEST0 */ + /* nothing to do */ + break; case 0x1a: /* CTEST2 */ s->ctest2 = val & LSI_CTEST2_PCICIE; break; |