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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-08 09:51:29 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-08 09:51:29 +0000
commitd0f1bb56583c5aa00c9bfcb3ac041644d0502c59 (patch)
treecf863f75e7513ed1a29d456a611c4bd2f6c9df8f /hw/sun4m.c
parent6edb873b653174c96ee91a9acb095559f134eec7 (diff)
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Use firmware configuration instead of NVRAM (initial patch by Aurelien Jarno)
Use firmware configuration device for boot device, kernel, initrd and kernel command line parameters on PPC, Sparc32 and Sparc64. Update OpenBIOS images to r479 which supports the change. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6777 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/sun4m.c')
-rw-r--r--hw/sun4m.c98
1 files changed, 41 insertions, 57 deletions
diff --git a/hw/sun4m.c b/hw/sun4m.c
index 21667c038e..681d9736e0 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -174,24 +174,9 @@ void DMA_register_channel (int nchan,
{
}
-static int nvram_boot_set(void *opaque, const char *boot_device)
+static int fw_cfg_boot_set(void *opaque, const char *boot_device)
{
- unsigned int i;
- uint8_t image[sizeof(ohwcfg_v3_t)];
- ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
- m48t59_t *nvram = (m48t59_t *)opaque;
-
- for (i = 0; i < sizeof(image); i++)
- image[i] = m48t59_read(nvram, i) & 0xff;
-
- pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
- boot_device);
- header->nboot_devices = strlen(boot_device) & 0xff;
- header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
-
- for (i = 0; i < sizeof(image); i++)
- m48t59_write(nvram, i, image[i]);
-
+ fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
return 0;
}
@@ -204,48 +189,11 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
unsigned int i;
uint32_t start, end;
uint8_t image[0x1ff0];
- ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
- struct sparc_arch_cfg *sparc_header;
struct OpenBIOS_nvpart_v1 *part_header;
memset(image, '\0', sizeof(image));
- // Try to match PPC NVRAM
- pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
- "QEMU_BIOS");
- header->struct_version = cpu_to_be32(3); /* structure v3 */
-
- header->nvram_size = cpu_to_be16(0x2000);
- header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
- header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
- pstrcpy((char *)header->arch, sizeof(header->arch), arch);
- header->nb_cpus = smp_cpus & 0xff;
- header->RAM0_base = 0;
- header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
- pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
- boot_devices);
- header->nboot_devices = strlen(boot_devices) & 0xff;
- header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
- header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
- if (cmdline) {
- pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
- header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
- header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
- }
- // XXX add initrd_image, initrd_size
- header->width = cpu_to_be16(width);
- header->height = cpu_to_be16(height);
- header->depth = cpu_to_be16(depth);
- if (nographic)
- header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
-
- header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
-
- // Architecture specific header
- start = sizeof(ohwcfg_v3_t);
- sparc_header = (struct sparc_arch_cfg *)&image[start];
- sparc_header->valid = 0;
- start += sizeof(struct sparc_arch_cfg);
+ start = 0;
// OpenBIOS nvram variables
// Variable partition
@@ -277,8 +225,6 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
for (i = 0; i < sizeof(image); i++)
m48t59_write(nvram, i, image[i]);
-
- qemu_register_boot_set(nvram_boot_set, nvram);
}
static void *slavio_intctl;
@@ -604,6 +550,18 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
+ if (kernel_cmdline) {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
+ pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
+ } else {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
enum {
@@ -1362,6 +1320,19 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
+ if (kernel_cmdline) {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
+ pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
+ } else {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
/* SPARCserver 1000 hardware initialisation */
@@ -1580,6 +1551,19 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
+ if (kernel_cmdline) {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
+ pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
+ } else {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
/* SPARCstation 2 hardware initialisation */