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| author | Avi Kivity <avi@redhat.com> | 2012-10-23 12:30:10 +0200 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2012-10-23 08:58:25 -0500 |
| commit | a8170e5e97ad17ca169c64ba87ae2f53850dab4c (patch) | |
| tree | 51182ed444f0d2bf282f6bdacef43f32e5adaadf /hw/smc91c111.c | |
| parent | 50d2b4d93f45a425f15ac88bc4ec352f5c6e0bc2 (diff) | |
| download | qemu-a8170e5e97ad17ca169c64ba87ae2f53850dab4c.tar.gz qemu-a8170e5e97ad17ca169c64ba87ae2f53850dab4c.tar.bz2 qemu-a8170e5e97ad17ca169c64ba87ae2f53850dab4c.zip | |
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific). Replace it with a finger-friendly,
standards conformant hwaddr.
Outstanding patchsets can be fixed up with the command
git rebase -i --exec 'find -name "*.[ch]"
| xargs s/target_phys_addr_t/hwaddr/g' origin
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/smc91c111.c')
| -rw-r--r-- | hw/smc91c111.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/hw/smc91c111.c b/hw/smc91c111.c index d6ef302c6d..4ceed01a1a 100644 --- a/hw/smc91c111.c +++ b/hw/smc91c111.c @@ -276,7 +276,7 @@ static void smc91c111_reset(DeviceState *dev) #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8) -static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, +static void smc91c111_writeb(void *opaque, hwaddr offset, uint32_t value) { smc91c111_state *s = (smc91c111_state *)opaque; @@ -451,7 +451,7 @@ static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset); } -static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset) +static uint32_t smc91c111_readb(void *opaque, hwaddr offset) { smc91c111_state *s = (smc91c111_state *)opaque; @@ -595,14 +595,14 @@ static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset) return 0; } -static void smc91c111_writew(void *opaque, target_phys_addr_t offset, +static void smc91c111_writew(void *opaque, hwaddr offset, uint32_t value) { smc91c111_writeb(opaque, offset, value & 0xff); smc91c111_writeb(opaque, offset + 1, value >> 8); } -static void smc91c111_writel(void *opaque, target_phys_addr_t offset, +static void smc91c111_writel(void *opaque, hwaddr offset, uint32_t value) { /* 32-bit writes to offset 0xc only actually write to the bank select @@ -612,7 +612,7 @@ static void smc91c111_writel(void *opaque, target_phys_addr_t offset, smc91c111_writew(opaque, offset + 2, value >> 16); } -static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset) +static uint32_t smc91c111_readw(void *opaque, hwaddr offset) { uint32_t val; val = smc91c111_readb(opaque, offset); @@ -620,7 +620,7 @@ static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset) return val; } -static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset) +static uint32_t smc91c111_readl(void *opaque, hwaddr offset) { uint32_t val; val = smc91c111_readw(opaque, offset); |