diff options
author | malc <av1474@comtv.ru> | 2009-10-01 22:20:47 +0400 |
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committer | malc <av1474@comtv.ru> | 2009-10-01 22:45:02 +0400 |
commit | 99a0949b720a0936da2052cb9a46db04ffc6db29 (patch) | |
tree | f9e39633853e35b49fc4465337cc196b9650866e /hw/parallel.c | |
parent | bc6291a1b95a2c4c546fde6e5cb4c68366f06649 (diff) | |
download | qemu-99a0949b720a0936da2052cb9a46db04ffc6db29.tar.gz qemu-99a0949b720a0936da2052cb9a46db04ffc6db29.tar.bz2 qemu-99a0949b720a0936da2052cb9a46db04ffc6db29.zip |
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.
Signed-off-by: malc <av1474@comtv.ru>
Diffstat (limited to 'hw/parallel.c')
-rw-r--r-- | hw/parallel.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/hw/parallel.c b/hw/parallel.c index faaaa0d9e4..12fe25bbbd 100644 --- a/hw/parallel.c +++ b/hw/parallel.c @@ -473,7 +473,7 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr) } /* Memory mapped interface */ -static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr) +static uint32_t parallel_mm_readb (void *opaque, a_target_phys_addr addr) { ParallelState *s = opaque; @@ -481,14 +481,14 @@ static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr) } static void parallel_mm_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ParallelState *s = opaque; parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF); } -static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr) +static uint32_t parallel_mm_readw (void *opaque, a_target_phys_addr addr) { ParallelState *s = opaque; @@ -496,14 +496,14 @@ static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr) } static void parallel_mm_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ParallelState *s = opaque; parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF); } -static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr) +static uint32_t parallel_mm_readl (void *opaque, a_target_phys_addr addr) { ParallelState *s = opaque; @@ -511,7 +511,7 @@ static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr) } static void parallel_mm_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ParallelState *s = opaque; @@ -531,7 +531,7 @@ static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = { }; /* If fd is zero, it means that the parallel device uses the console */ -ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr) +ParallelState *parallel_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq, CharDriverState *chr) { ParallelState *s; int io_sw; |