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| author | Scott Wood <scottwood@freescale.com> | 2013-01-21 15:53:52 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-01-25 22:02:56 +0100 |
| commit | 03274d44f655f7b822e845e79fa32b261cdb0774 (patch) | |
| tree | 682fbf16771bfd94a451315071c083f9dd4f57cd /hw/openpic.c | |
| parent | f40c360c0da020a1a478f8e60dd205d7412bc315 (diff) | |
| download | qemu-03274d44f655f7b822e845e79fa32b261cdb0774.tar.gz qemu-03274d44f655f7b822e845e79fa32b261cdb0774.tar.bz2 qemu-03274d44f655f7b822e845e79fa32b261cdb0774.zip | |
openpic: fix timer address decoding
The timer memory range begins at 0x10f0, so that address 0x1120 shows
up as 0x30, 0x1130 shows up as 0x40, etc. However, the address
decoding (other than TFRR) is not adjusted for this, causing the
wrong registers to be accessed.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/openpic.c')
| -rw-r--r-- | hw/openpic.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/hw/openpic.c b/hw/openpic.c index a4488c2d44..0a4379ff5c 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -792,19 +792,23 @@ static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, OpenPICState *opp = opaque; int idx; + addr += 0x10f0; + DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", __func__, addr, val); if (addr & 0xF) { return; } - idx = (addr >> 6) & 0x3; - addr = addr & 0x30; - if (addr == 0x0) { + if (addr == 0x10f0) { /* TFRR */ opp->tfrr = val; return; } + + idx = (addr >> 6) & 0x3; + addr = addr & 0x30; + switch (addr & 0x30) { case 0x00: /* TCCR */ break; |