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author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-21 20:40:22 +0000 |
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committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-21 20:40:22 +0000 |
commit | afbb5194d430adc0f1f3a63ea627bc93e8d17c56 (patch) | |
tree | 4e89b563a2287d396af41db81d2ea77ceea7337c /hw/omap.h | |
parent | 51fec3cc7eb7a9c8e1be2f2bb971db303d17ea61 (diff) | |
download | qemu-afbb5194d430adc0f1f3a63ea627bc93e8d17c56.tar.gz qemu-afbb5194d430adc0f1f3a63ea627bc93e8d17c56.tar.bz2 qemu-afbb5194d430adc0f1f3a63ea627bc93e8d17c56.zip |
Handle on-chip DMA controllers in one place, convert OMAP DMA to use it.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4920 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/omap.h')
-rw-r--r-- | hw/omap.h | 12 |
1 files changed, 6 insertions, 6 deletions
@@ -417,14 +417,14 @@ enum omap_dma_model { omap_dma_4, }; -struct omap_dma_s; -struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, +struct soc_dma_s; +struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, enum omap_dma_model model); -struct omap_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs, +struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs, struct omap_mpu_state_s *mpu, int fifo, int chans, omap_clk iclk, omap_clk fclk); -void omap_dma_reset(struct omap_dma_s *s); +void omap_dma_reset(struct soc_dma_s *s); struct dma_irq_map { int ih; @@ -494,7 +494,7 @@ struct omap_dma_lcd_channel_s { ram_addr_t phys_framebuffer[2]; qemu_irq irq; struct omap_mpu_state_s *mpu; -} *omap_dma_get_lcdch(struct omap_dma_s *s); +} *omap_dma_get_lcdch(struct soc_dma_s *s); /* * DMA request numbers for OMAP1 @@ -882,7 +882,7 @@ struct omap_mpu_state_s { /* MPU private TIPB peripherals */ struct omap_intr_handler_s *ih[2]; - struct omap_dma_s *dma; + struct soc_dma_s *dma; struct omap_mpu_timer_s *timer[3]; struct omap_watchdog_timer_s *wdt; |