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authorPeter Maydell <peter.maydell@linaro.org>2014-09-12 15:12:26 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-09-12 15:12:26 +0100
commit4c24f4004089a308c5de8ed720cf6bd1746aedd8 (patch)
treed83f318edd5b987a94d0a16ed8a25a215c645fca /hw/core
parent6cd14054b67774cc58a51fca6660cfa1d3c08059 (diff)
parent92df845070290236d1b28b03453deec1ae9c4263 (diff)
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140912' into staging
target-arm: * add "linux,stdout-path" to the virt DTB * fix a long standing bug with IRQ disabling on Cortex-M CPUs * implement input interrupt logic in the PL061 * fix failure to load correct SP/PC on reset of Cortex-M CPUs if the vector table is not in a ROM-blob-in-RAM * provide flash devices for boot ROMs in the virt board * implement architectural watchpoints * fix misimplementation of Inner Shareable TLB operations that caused instability of guests in TCG SMP configurations * configure PL011 and PL031 in the virt board correctly with level-triggered interrupts rather than edge-triggered * support providing a device tree blob to ROM (firmware) images as well as to kernels # gpg: Signature made Fri 12 Sep 2014 14:19:08 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140912: (23 commits) hw/arm/boot: enable DTB support when booting ELF images hw/arm/boot: load device tree to base of DRAM if no -kernel option was passed hw/arm/boot: pass an address limit to and return size from load_dtb() hw/arm/boot: load DTB as a ROM image hw/arm/virt: fix pl011 and pl031 irq flags target-arm: Make *IS TLB maintenance ops affect all CPUs target-arm: Push legacy wildcard TLB ops back into v6 target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0 target-arm: Remove comment about MDSCR_EL1 being dummy implementation target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32 target-arm: Implement handling of fired watchpoints target-arm: Move extended_addresses_enabled() to internals.h target-arm: Implement setting of watchpoints cpu-exec: Make debug_excp_handler a QOM CPU method exec.c: Record watchpoint fault address and direction exec.c: Provide full set of dummy wp remove functions in user-mode exec.c: Relax restrictions on watchpoint length and alignment hw/arm/virt: Provide flash devices for boot ROMs target-arm: Fix broken indentation in arm_cpu_reest() target-arm: Fix resetting issues on ARMv7-M CPUs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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