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author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-10-21 11:28:46 +0000 |
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committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-10-21 11:28:46 +0000 |
commit | 3d7b417e13152587df587fe58789740c3ef7abb9 (patch) | |
tree | 824bf571e3bad076986e5144f6834ffd032d77f1 /gdbstub.c | |
parent | d75a0b97e0e9bfcd73dd2ef081ba06e53932b42d (diff) | |
download | qemu-3d7b417e13152587df587fe58789740c3ef7abb9.tar.gz qemu-3d7b417e13152587df587fe58789740c3ef7abb9.tar.bz2 qemu-3d7b417e13152587df587fe58789740c3ef7abb9.zip |
target-ppc: Convert XER accesses to TCG
Define XER bits as a single register and access them individually to
avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit
registers).
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'gdbstub.c')
-rw-r--r-- | gdbstub.c | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -445,7 +445,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) } case 67: GET_REGL(env->lr); case 68: GET_REGL(env->ctr); - case 69: GET_REG32(ppc_load_xer(env)); + case 69: GET_REGL(env->xer); case 70: GET_REG32(0); /* fpscr */ } } @@ -485,8 +485,8 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) env->ctr = ldtul_p(mem_buf); return sizeof(target_ulong); case 69: - ppc_store_xer(env, ldl_p(mem_buf)); - return 4; + env->xer = ldtul_p(mem_buf); + return sizeof(target_ulong); case 70: /* fpscr */ return 4; |