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| author | Richard Henderson <rth@twiddle.net> | 2014-08-06 11:48:48 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@redhat.com> | 2014-09-29 14:55:27 -0400 |
| commit | 90379ca84ebe94b0adc08794d90ea1e196b2a724 (patch) | |
| tree | c55ace94c6a479b4ecf8f01042553d5712aaa93c /disas | |
| parent | 609ac1e16473e7dfc4dc54becde4b1902dbdf919 (diff) | |
| download | qemu-90379ca84ebe94b0adc08794d90ea1e196b2a724.tar.gz qemu-90379ca84ebe94b0adc08794d90ea1e196b2a724.tar.bz2 qemu-90379ca84ebe94b0adc08794d90ea1e196b2a724.zip | |
tcg-sparc: Use ADDXC in addsub2_i64
On T4 and newer Sparc chips we have an add-with-carry insn
that takes its input from %xcc instead of %icc.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'disas')
| -rw-r--r-- | disas/sparc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/disas/sparc.c b/disas/sparc.c index 8eb22e6fc3..092e1b6098 100644 --- a/disas/sparc.c +++ b/disas/sparc.c @@ -2042,6 +2042,9 @@ IMPDEP ("impdep2", 0x37), #undef IMPDEP +{ "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, v9b }, +{ "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, v9b }, + }; static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); |