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authorMax Filippov <jcmvbkbc@gmail.com>2011-10-16 02:56:46 +0400
committerBlue Swirl <blauwirbel@gmail.com>2011-10-16 10:42:21 +0000
commit0200db650e6386d44ba2a707d9f22ddf72681cf7 (patch)
tree61c8bda545e9b38dd3b3f4751b4574d6acdee691 /Makefile.target
parent342407fd958f8f5546527e6fecaa501700fb03e5 (diff)
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target-xtensa: add Avnet LX60/LX110/LX200 boards
These boards carry similar hardware: SDRAM (48M for LX110, 64M for LX60, 96M for LX200), 16 Mbyte FLASH, FPGA, 10/100 Mbps Ethernet PHY and 16550 UART. FPGA may be loaded with almost any Tensilica processor. It is also used to implement Ethernet MAC, e.g. OpenCores 10/100 Mbps Ethernet MAC and LED/DIP switches access. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'Makefile.target')
-rw-r--r--Makefile.target1
1 files changed, 1 insertions, 0 deletions
diff --git a/Makefile.target b/Makefile.target
index 752221c44b..3d942283a3 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -371,6 +371,7 @@ obj-alpha-y += alpha_pci.o alpha_dp264.o alpha_typhoon.o
obj-xtensa-y += xtensa_pic.o
obj-xtensa-y += xtensa_sim.o
+obj-xtensa-y += xtensa_lx60.o
obj-xtensa-y += xtensa-semi.o
obj-xtensa-y += core-dc232b.o
obj-xtensa-y += core-fsf.o