diff options
| author | Alexander Graf <agraf@suse.de> | 2014-01-04 22:15:50 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-08 19:07:21 +0000 |
| commit | 6163f868c9284a204ea108238f1812ad50c6bf17 (patch) | |
| tree | 33765021b0afcf3227d96a57eef46c1fd8e4133a | |
| parent | 6a30667fb77601b47501172218c7eabd0086c375 (diff) | |
| download | qemu-6163f868c9284a204ea108238f1812ad50c6bf17.tar.gz qemu-6163f868c9284a204ea108238f1812ad50c6bf17.tar.bz2 qemu-6163f868c9284a204ea108238f1812ad50c6bf17.zip | |
target-arm: A64: Add fmov (scalar, immediate) instruction
This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.
Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, rebase and use new infrastructure.]
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target-arm/translate-a64.c | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 84497dc308..bb36a66955 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -3479,7 +3479,37 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn) */ static void disas_fp_imm(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + int rd = extract32(insn, 0, 5); + int imm8 = extract32(insn, 13, 8); + int is_double = extract32(insn, 22, 2); + uint64_t imm; + TCGv_i64 tcg_res; + + if (is_double > 1) { + unallocated_encoding(s); + return; + } + + /* The imm8 encodes the sign bit, enough bits to represent + * an exponent in the range 01....1xx to 10....0xx, + * and the most significant 4 bits of the mantissa; see + * VFPExpandImm() in the v8 ARM ARM. + */ + if (is_double) { + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | + extract32(imm8, 0, 6); + imm <<= 48; + } else { + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | + (extract32(imm8, 0, 6) << 3); + imm <<= 16; + } + + tcg_res = tcg_const_i64(imm); + write_fp_dreg(s, rd, tcg_res); + tcg_temp_free_i64(tcg_res); } /* C3.6.29 Floating point <-> fixed point conversions |