diff options
| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2014-02-25 16:38:19 -0800 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2014-02-26 14:54:45 +1000 |
| commit | 05a738c4eca9e809226dec4b83624a3bad8066ee (patch) | |
| tree | 8ca6156ae7baf811c4e5bd3a0bf491c159f59ab4 | |
| parent | aa0d1f448871314bfc535da97eb003fe7766d4c2 (diff) | |
| download | qemu-05a738c4eca9e809226dec4b83624a3bad8066ee.tar.gz qemu-05a738c4eca9e809226dec4b83624a3bad8066ee.tar.bz2 qemu-05a738c4eca9e809226dec4b83624a3bad8066ee.zip | |
microblaze/s3adsp_1800: Define macros for irq map
Define macros for the interrupt map for the sake of self documentation.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| -rw-r--r-- | hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index f50021506c..a4877a676a 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -48,6 +48,10 @@ #define UARTLITE_BASEADDR 0x84000000 #define ETHLITE_BASEADDR 0x81000000 +#define TIMER_IRQ 0 +#define ETHLITE_IRQ 1 +#define UARTLITE_IRQ 3 + static void machine_cpu_reset(MicroBlazeCPU *cpu) { CPUMBState *env = &cpu->env; @@ -99,7 +103,8 @@ petalogix_s3adsp1800_init(QEMUMachineInitArgs *args) irq[i] = qdev_get_gpio_in(dev, i); } - sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[3]); + sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, + irq[UARTLITE_IRQ]); /* 2 timers at irq 2 @ 62 Mhz. */ xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000); xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0); |