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| author | Richard Henderson <rth@twiddle.net> | 2011-04-10 10:31:20 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@anchor.twiddle.net> | 2011-05-31 10:18:04 -0700 |
| commit | b9bec751c8c8b08d8055da32306eb105db03031b (patch) | |
| tree | 79b63e53f596747e6c4698c408ee352637e39ee4 | |
| parent | 8d6df264f130a21d08cde320a9f3bccbdd7b532c (diff) | |
| download | qemu-b9bec751c8c8b08d8055da32306eb105db03031b.tar.gz qemu-b9bec751c8c8b08d8055da32306eb105db03031b.tar.bz2 qemu-b9bec751c8c8b08d8055da32306eb105db03031b.zip | |
target-alpha: Disassemble EV6 PALcode instructions.
The QEMU emulation PALcode will use EV6 PALcode insns regardless
of the "real" cpu instruction set being emulated.
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | alpha-dis.c | 4 | ||||
| -rw-r--r-- | dis-asm.h | 3 | ||||
| -rw-r--r-- | disas.c | 2 |
3 files changed, 4 insertions, 5 deletions
diff --git a/alpha-dis.c b/alpha-dis.c index 8a2411e4d5..ae331b35b8 100644 --- a/alpha-dis.c +++ b/alpha-dis.c @@ -238,10 +238,6 @@ extern const unsigned alpha_num_operands; #define AXP_REG_SP 30 #define AXP_REG_ZERO 31 -#define bfd_mach_alpha_ev4 0x10 -#define bfd_mach_alpha_ev5 0x20 -#define bfd_mach_alpha_ev6 0x30 - enum bfd_reloc_code_real { BFD_RELOC_23_PCREL_S2, BFD_RELOC_ALPHA_HINT @@ -184,6 +184,9 @@ enum bfd_architecture #define bfd_mach_sh5 0x50 bfd_arch_alpha, /* Dec Alpha */ #define bfd_mach_alpha 1 +#define bfd_mach_alpha_ev4 0x10 +#define bfd_mach_alpha_ev5 0x20 +#define bfd_mach_alpha_ev6 0x30 bfd_arch_arm, /* Advanced Risc Machines ARM */ #define bfd_mach_arm_unknown 0 #define bfd_mach_arm_2 1 @@ -205,7 +205,7 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) disasm_info.mach = bfd_mach_sh4; print_insn = print_insn_sh; #elif defined(TARGET_ALPHA) - disasm_info.mach = bfd_mach_alpha; + disasm_info.mach = bfd_mach_alpha_ev6; print_insn = print_insn_alpha; #elif defined(TARGET_CRIS) if (flags != 32) { |