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authorAndreas Färber <afaerber@suse.de>2013-06-21 22:09:01 +0200
committerAndreas Färber <afaerber@suse.de>2013-07-09 21:33:03 +0200
commit467215c20f4befed253696dd6910839bacf75837 (patch)
treeaa49d175d188a318ea121711039fbd1e6a0b3f4c
parent7fd2592dbcc0130e9999a739867a1b539c5ee853 (diff)
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target-i386: Change gen_intermediate_code_internal() argument to X86CPU
Also use bool type while at it. Prepares for moving singlestep_enabled field to CPUState. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
-rw-r--r--target-i386/translate.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 14b0298749..6550c27798 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8251,10 +8251,11 @@ void optimize_flags_init(void)
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
basic block 'tb'. If search_pc is TRUE, also generate PC
information for each intermediate instruction. */
-static inline void gen_intermediate_code_internal(CPUX86State *env,
+static inline void gen_intermediate_code_internal(X86CPU *cpu,
TranslationBlock *tb,
- int search_pc)
+ bool search_pc)
{
+ CPUX86State *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;
uint16_t *gen_opc_end;
@@ -8428,12 +8429,12 @@ static inline void gen_intermediate_code_internal(CPUX86State *env,
void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
{
- gen_intermediate_code_internal(env, tb, 0);
+ gen_intermediate_code_internal(x86_env_get_cpu(env), tb, false);
}
void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
{
- gen_intermediate_code_internal(env, tb, 1);
+ gen_intermediate_code_internal(x86_env_get_cpu(env), tb, true);
}
void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos)