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| author | Seung-Woo Kim <sw0312.kim@samsung.com> | 2019-10-22 19:45:52 +0900 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2019-10-23 10:19:43 +0900 |
| commit | a6b12043d4cd461d3700388a073f97ed90044834 (patch) | |
| tree | bb9d9d48fe1c0c2043a6eca82b849be805c6659d | |
| parent | defa77f39f76ec487a1cca3002b7d317de1c7c9a (diff) | |
| download | linux-4.9-exynos9110-a6b12043d4cd461d3700388a073f97ed90044834.tar.gz linux-4.9-exynos9110-a6b12043d4cd461d3700388a073f97ed90044834.tar.bz2 linux-4.9-exynos9110-a6b12043d4cd461d3700388a073f97ed90044834.zip | |
soc: samsung: cal-if: exynos9110: remove a clock for unassigned block
From exynos9110 clock sfr, sfr of BLK_MODEM is set as just 0 and
that means it is not assigned. Accessing clock for the block
causes memory abort accessing wrong address. So remove the clock
for unassigned modem block.
Change-Id: Id880ed48ef8d01f4d8c348642fdcffc4004997fd
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
| -rw-r--r-- | drivers/soc/samsung/cal-if/exynos9110/cmucal-node.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/soc/samsung/cal-if/exynos9110/cmucal-node.c b/drivers/soc/samsung/cal-if/exynos9110/cmucal-node.c index e9845e461d45..5c161ff56d49 100644 --- a/drivers/soc/samsung/cal-if/exynos9110/cmucal-node.c +++ b/drivers/soc/samsung/cal-if/exynos9110/cmucal-node.c @@ -1007,7 +1007,10 @@ struct cmucal_gate cmucal_gate_list[] = { CLK_GATE(CLK_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), CLK_GATE(CLK_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), CLK_GATE(CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), +#ifdef USE_MODEM_BLOCK + /* currently modem block sfr register address is not properly set */ CLK_GATE(CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK, AP2CP_SHARED0_PLL_CLK, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), +#endif CLK_GATE(CLK_BLK_PERI_UID_RSTnSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK, OSCCLK_PERI, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), CLK_GATE(GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), CLK_GATE(GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |