soc: samsung: cal-if: exynos9110: remove clocks for secure worldsubmit/tizen_5.5/20191115.014019submit/tizen/20191031.111959submit/tizen/20191031.023155submit/tizen/20191031.012258accepted/tizen/unified/20191101.042028accepted/tizen/5.5/unified/20191115.093732tizen_5.5_tv

In exynos9110, some clocks are protected by trustzone secure world,
and accessing them causes system abort. Not to access the clocks from
kernel in normal world, remove the clocks protected by secure
world including ispp, vts, mfcmscl, g3dp, chubp.

Change-Id: I6ef4de7bbb77f50492cc34f90f7e012fa55395cf
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

1 files changed, 46 insertions, 0 deletions

diff --git a/drivers/soc/samsung/cal-if/exynos9110/cmucal-node.c b/drivers/soc/samsung/cal-if/exynos9110/cmucal-node.c
index 5c161ff56d49..82b2d8b609d5 100644
--- a/drivers/soc/samsung/cal-if/exynos9110/cmucal-node.c
+++ b/drivers/soc/samsung/cal-if/exynos9110/cmucal-node.c
@@ -307,7 +307,9 @@ enum clk_id cmucal_mux_clk_peri_spi_parents[] = {
 };
 enum clk_id cmucal_mux_clk_vts_bus_parents[] = {
 	MUX_CLK_RCO_VTS_USER,
+#ifdef USE_VTS_IN_NORMAL_WORLD
 	MUX_CLKCMU_VTS_BUS_USER,
+#endif
 };
 enum clk_id cmucal_mux_clkcmu_apm_bus_user_parents[] = {
 	OSCCLK_RCO_APM,
@@ -427,11 +429,13 @@ struct cmucal_mux cmucal_mux_list[] = {
 	CLK_MUX(MUX_CLK_APM_BUS, cmucal_mux_clk_apm_bus_parents, CLK_CON_MUX_MUX_CLK_APM_BUS_SELECT, CLK_CON_MUX_MUX_CLK_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLKCMU_CHUB_BUS, cmucal_mux_clkcmu_chub_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLKCMU_VTS_BUS, cmucal_mux_clkcmu_vts_bus_parents, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_CHUBP_IN_NORMAL_WORLD
 	CLK_MUX(MUX_CLK_CHUB_BUS, cmucal_mux_clk_chub_bus_parents, CLK_CON_MUX_MUX_CLK_CHUB_BUS_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_BUS_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(CLK_CHUB_TIMER_FCLK, cmucal_clk_chub_timer_fclk_parents, CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_SELECT, CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_BUSY, CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLK_CHUB_USI0, cmucal_mux_clk_chub_usi0_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI0_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI0_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLK_CHUB_I2C0, cmucal_mux_clk_chub_i2c0_parents, CLK_CON_MUX_MUX_CLK_CHUB_I2C0_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_I2C0_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_I2C0_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLK_CHUB_I2C1, cmucal_mux_clk_chub_i2c1_parents, CLK_CON_MUX_MUX_CLK_CHUB_I2C1_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_I2C1_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_I2C1_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_MUX(MUX_CLK_CMGP_ADC, cmucal_mux_clk_cmgp_adc_parents, CLK_CON_MUX_MUX_CLK_CMGP_ADC_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_ADC_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLK_CMGP_I2C0, cmucal_mux_clk_cmgp_i2c0_parents, CLK_CON_MUX_MUX_CLK_CMGP_I2C0_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C0_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C0_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLK_CMGP_USI0, cmucal_mux_clk_cmgp_usi0_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI0_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI0_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING),
@@ -477,7 +481,9 @@ struct cmucal_mux cmucal_mux_list[] = {
 	CLK_MUX(MUX_MIF_CMUREF, cmucal_mux_mif_cmuref_parents, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLK_PERI_USI00_USI, cmucal_mux_clk_peri_usi00_usi_parents, CLK_CON_MUX_MUX_CLK_PERI_USI00_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERI_USI00_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERI_USI00_USI_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLK_PERI_SPI, cmucal_mux_clk_peri_spi_parents, CLK_CON_MUX_MUX_CLK_PERI_SPI_SELECT, CLK_CON_MUX_MUX_CLK_PERI_SPI_BUSY, CLK_CON_MUX_MUX_CLK_PERI_SPI_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_VTS_IN_NORMAL_WORLD
 	CLK_MUX(MUX_CLK_VTS_BUS, cmucal_mux_clk_vts_bus_parents, CLK_CON_MUX_MUX_CLK_VTS_BUS_SELECT, CLK_CON_MUX_MUX_CLK_VTS_BUS_BUSY, CLK_CON_MUX_MUX_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_MUX(APM_CMU_APM_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
 	CLK_MUX(CHUB_CMU_CHUB_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
 	CLK_MUX(CMGP_CMU_CMGP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
@@ -509,17 +515,25 @@ struct cmucal_mux cmucal_mux_list[] = {
 	CLK_MUX(MUX_CLKCMU_FSYS_MMC_CARD_USER, cmucal_mux_clkcmu_fsys_mmc_card_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLKCMU_FSYS_MMC_EMBD_USER, cmucal_mux_clkcmu_fsys_mmc_embd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLKCMU_FSYS_USB20DRD_USER, cmucal_mux_clkcmu_fsys_usb20drd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_USB20DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_USB20DRD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_USB20DRD_USER_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_G3DP_IN_NORMAL_WORLD
 	CLK_MUX(MUX_CLKCMU_G3D_BUS_USER, cmucal_mux_clkcmu_g3d_bus_user_parents, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_G3D_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
+#endif
+#ifdef USE_ISPP_IN_NORMAL_WORLD
 	CLK_MUX(MUX_CLKCMU_IS_BUS_USER, cmucal_mux_clkcmu_is_bus_user_parents, PLL_CON0_MUX_CLKCMU_IS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_IS_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_IS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLKCMU_IS_VRA_USER, cmucal_mux_clkcmu_is_vra_user_parents, PLL_CON0_MUX_CLKCMU_IS_VRA_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_IS_VRA_USER_BUSY, PLL_CON2_MUX_CLKCMU_IS_VRA_USER_ENABLE_AUTOMATIC_CLKGATING),
+#endif
+#ifdef USE_MFCMSCL_IN_NORMAL_WORLD
 	CLK_MUX(MUX_CLKCMU_MFCMSCL_MSCL_USER, cmucal_mux_clkcmu_mfcmscl_mscl_user_parents, PLL_CON0_MUX_CLKCMU_MFCMSCL_MSCL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFCMSCL_MSCL_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFCMSCL_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLKCMU_MFCMSCL_MFC_USER, cmucal_mux_clkcmu_mfcmscl_mfc_user_parents, PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFCMSCL_MFC_USER_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_MUX(MUX_CLKCMU_MIF_BUSP_USER, cmucal_mux_clkcmu_mif_busp_user_parents, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLKCMU_PERI_BUS_USER, cmucal_mux_clkcmu_peri_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLKCMU_PERI_IP_USER, cmucal_mux_clkcmu_peri_ip_user_parents, PLL_CON0_MUX_CLKCMU_PERI_IP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_IP_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_IP_USER_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLKCMU_PERI_UART_USER, cmucal_mux_clkcmu_peri_uart_user_parents, PLL_CON0_MUX_CLKCMU_PERI_UART_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_UART_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_UART_USER_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_MUX(MUX_CLKCMU_VTS_BUS_USER, cmucal_mux_clkcmu_vts_bus_user_parents, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_VTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_VTS_IN_NORMAL_WORLD
 	CLK_MUX(MUX_CLK_RCO_VTS_USER, cmucal_mux_clk_rco_vts_user_parents, PLL_CON0_MUX_CLK_RCO_VTS_USER_MUX_SEL, PLL_CON0_MUX_CLK_RCO_VTS_USER_BUSY, PLL_CON2_MUX_CLK_RCO_VTS_USER_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 };
 
 /*====================The section of DIVs===================*/
@@ -530,10 +544,12 @@ struct cmucal_div cmucal_div_list[] = {
 	CLK_DIV(DIV_CLK_APM_BUS, MUX_CLK_APM_BUS, CLK_CON_DIV_DIV_CLK_APM_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_BUS_BUSY, CLK_CON_DIV_DIV_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(CLKCMU_VTS_BUS, GATE_CLKCMU_VTS_BUS, CLK_CON_DIV_CLKCMU_VTS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_VTS_BUS_BUSY, CLK_CON_DIV_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(CLKCMU_CHUB_BUS, GATE_CLKCMU_CHUB_BUS, CLK_CON_DIV_CLKCMU_CHUB_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CHUB_BUS_BUSY, CLK_CON_DIV_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_CHUBP_IN_NORMAL_WORLD
 	CLK_DIV(DIV_CLK_CHUB_BUS, MUX_CLK_CHUB_BUS, CLK_CON_DIV_DIV_CLK_CHUB_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_BUS_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_CHUB_USI0, MUX_CLK_CHUB_USI0, CLK_CON_DIV_DIV_CLK_CHUB_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI0_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_CHUB_I2C0, MUX_CLK_CHUB_I2C0, CLK_CON_DIV_DIV_CLK_CHUB_I2C0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_I2C0_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_I2C0_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_CHUB_I2C1, MUX_CLK_CHUB_I2C1, CLK_CON_DIV_DIV_CLK_CHUB_I2C1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_I2C1_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_I2C1_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_DIV(DIV_CLK_CMGP_ADC, CLKCMU_CMGP_BUS, CLK_CON_DIV_DIV_CLK_CMGP_ADC_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_ADC_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_CMGP_I2C0, MUX_CLK_CMGP_I2C0, CLK_CON_DIV_DIV_CLK_CMGP_I2C0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C0_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C0_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_CMGP_USI0, MUX_CLK_CMGP_USI0, CLK_CON_DIV_DIV_CLK_CMGP_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI0_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING),
@@ -595,17 +611,25 @@ struct cmucal_div cmucal_div_list[] = {
 	CLK_DIV(DIV_CLK_AUD_FM, MUX_CLK_AUD_FM, CLK_CON_DIV_DIV_CLK_AUD_FM_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_AUD_DMIC, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_DMIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_DMIC_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DMIC_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_AUD_MCLK, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_MCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_MCLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_MCLK_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_G3DP_IN_NORMAL_WORLD
 	CLK_DIV(DIV_CLK_G3D_BUSP, MUX_CLKCMU_G3D_BUS_USER, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING),
+#endif
+#ifdef USE_ISPP_IN_NORMAL_WORLD
 	CLK_DIV(DIV_CLK_IS_BUSP, MUX_CLKCMU_IS_BUS_USER, CLK_CON_DIV_DIV_CLK_IS_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_IS_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_IS_BUSP_ENABLE_AUTOMATIC_CLKGATING),
+#endif
+#ifdef USE_MFCMSCL_IN_NORMAL_WORLD
 	CLK_DIV(DIV_CLK_MFCMSCL_BUSP, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_DIV(DIV_CLK_PERI_HSI2C, GATE_CLK_PERI_HSI2C, CLK_CON_DIV_DIV_CLK_PERI_HSI2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_HSI2C_BUSY, CLK_CON_DIV_DIV_CLK_PERI_HSI2C_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_PERI_SPI, MUX_CLK_PERI_SPI, CLK_CON_DIV_DIV_CLK_PERI_SPI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_SPI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_SPI_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_PERI_USI00_I2C, GATE_CLK_PERI_USI00_I2C, CLK_CON_DIV_DIV_CLK_PERI_USI00_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI00_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI00_I2C_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_PERI_USI00_USI, MUX_CLK_PERI_USI00_USI, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_VTS_IN_NORMAL_WORLD
 	CLK_DIV(DIV_CLK_VTS_DMIC_IF, MUX_CLK_RCO_VTS_USER, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_VTS_DMIC, DIV_CLK_VTS_DMIC_IF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_VTS_DMIC_IF_DIV2, DIV_CLK_VTS_DMIC_IF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_DIV(DIV_CLK_VTS_BUS, MUX_CLK_VTS_BUS, CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 };
 
 /*====================The section of GATEs===================*/
@@ -663,6 +687,7 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(CLK_BLK_APM_UID_RSTnSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_APM, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_APM_UID_APBIF_GPIO_CMGPALV_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_CMGPALV_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_CMGPALV_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_CMGPALV_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_CHUBP_IN_NORMAL_WORLD
 	CLK_GATE(CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CHUB_UID_BAAW_D_CHUB_IPCLKPORT_I_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_BAAW_D_CHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_BAAW_D_CHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_BAAW_D_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CHUB_UID_BAAW_P_APM_CHUB_IPCLKPORT_I_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_BAAW_P_APM_CHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_BAAW_P_APM_CHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_BAAW_P_APM_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
@@ -674,8 +699,10 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(GOUT_BLK_CHUB_UID_PDMA_CHUB_IPCLKPORT_ACLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PDMA_CHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PDMA_CHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PDMA_CHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_i_PCLK_S0, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_GATE(CLK_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_CHUB__ALV, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(CLK_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK, RTCCLK_CHUB__ALV, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_CHUBP_IN_NORMAL_WORLD
 	CLK_GATE(GOUT_BLK_CHUB_UID_SWEEPER_D_CHUB_IPCLKPORT_ACLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SWEEPER_D_CHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SWEEPER_D_CHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SWEEPER_D_CHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CHUB_UID_SWEEPER_P_APM_CHUB_IPCLKPORT_ACLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SWEEPER_P_APM_CHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SWEEPER_P_APM_CHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SWEEPER_P_APM_CHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
@@ -694,9 +721,12 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(GOUT_BLK_CHUB_UID_CHUB_RTC_APBIF_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CHUB_RTC_APBIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CHUB_RTC_APBIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CHUB_RTC_APBIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CHUB_UID_GPIO_CMGPALV_CHUB_APBIF_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_GPIO_CMGPALV_CHUB_APBIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_GPIO_CMGPALV_CHUB_APBIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_GPIO_CMGPALV_CHUB_APBIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK, DIV_CLK_CHUB_USI0, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_GATE(GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_I2C0_IPCLKPORT_CLK, DIV_CLK_CHUB_I2C0, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_CHUBP_IN_NORMAL_WORLD
 	CLK_GATE(GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_I2C1_IPCLKPORT_CLK, DIV_CLK_CHUB_I2C1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK, CLK_CHUB_TIMER_FCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_GATE(CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
@@ -921,9 +951,12 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(GOUT_BLK_FSYS_UID_US_64to128_FSYS_IPCLKPORT_aclk, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_US_64TO128_FSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_US_64TO128_FSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_US_64TO128_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(CLK_BLK_FSYS_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_50, MUX_CLKCMU_FSYS_USB20DRD_USER, CLK_CON_GAT_CLK_BLK_FSYS_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_50_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_50_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_50_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(CLK_BLK_FSYS_UID_USB20DRD_TOP_IPCLKPORT_I_USB20_PHY_REFCLK_26, OSCCLK_FSYS, CLK_CON_GAT_CLK_BLK_FSYS_UID_USB20DRD_TOP_IPCLKPORT_I_USB20_PHY_REFCLK_26_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_USB20DRD_TOP_IPCLKPORT_I_USB20_PHY_REFCLK_26_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_USB20DRD_TOP_IPCLKPORT_I_USB20_PHY_REFCLK_26_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_G3DP_IN_NORMAL_WORLD
 	CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_G3DP_IN_NORMAL_WORLD
 	CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_G3D_BUS_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, MUX_CLKCMU_G3D_BUS_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
@@ -931,8 +964,12 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_G3D_BUS_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM, MUX_CLKCMU_G3D_BUS_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
+#endif
+#ifdef USE_ISPP_IN_NORMAL_WORLD
 	CLK_GATE(CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK, DIV_CLK_IS_BUSP, CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_GATE(GOUT_BLK_IS_UID_RSTnSYNC_CLK_IS_BUSP_IPCLKPORT_CLK, DIV_CLK_IS_BUSP, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_ISPP_IN_NORMAL_WORLD
 	CLK_GATE(GOUT_BLK_IS_UID_RSTnSYNC_CLK_IS_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_IS_BUS_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_IS_UID_RSTnSYNC_CLK_IS_VRA_IPCLKPORT_CLK, MUX_CLKCMU_IS_VRA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK, DIV_CLK_IS_BUSP, CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
@@ -968,6 +1005,8 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(GOUT_BLK_IS_UID_is3p21p0_IS_IPCLKPORT_APB_ASYNC_CSIS_DMA_PCLKS, DIV_CLK_IS_BUSP, CLK_CON_GAT_GOUT_BLK_IS_UID_IS3P21P0_IS_IPCLKPORT_APB_ASYNC_CSIS_DMA_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS3P21P0_IS_IPCLKPORT_APB_ASYNC_CSIS_DMA_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS3P21P0_IS_IPCLKPORT_APB_ASYNC_CSIS_DMA_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_IS_UID_is3p21p0_IS_IPCLKPORT_ACLK_CSIS_DMA, MUX_CLKCMU_IS_BUS_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS3P21P0_IS_IPCLKPORT_ACLK_CSIS_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS3P21P0_IS_IPCLKPORT_ACLK_CSIS_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS3P21P0_IS_IPCLKPORT_ACLK_CSIS_DMA_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_IS_UID_is3p21p0_IS_IPCLKPORT_APB_ASYNC_VRA_PCLKM, MUX_CLKCMU_IS_VRA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS3P21P0_IS_IPCLKPORT_APB_ASYNC_VRA_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS3P21P0_IS_IPCLKPORT_APB_ASYNC_VRA_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS3P21P0_IS_IPCLKPORT_APB_ASYNC_VRA_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
+#endif
+#ifdef USE_MFCMSCL_IN_NORMAL_WORLD
 	CLK_GATE(CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK, DIV_CLK_MFCMSCL_BUSP, CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_PPMU_MFCMSCL_IPCLKPORT_PCLK, DIV_CLK_MFCMSCL_BUSP, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_PPMU_MFCMSCL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_PPMU_MFCMSCL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_PPMU_MFCMSCL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
@@ -975,7 +1014,9 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_RSTnSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_RSTnSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_RSTnSYNC_CLK_MFCMSCL_BUSP_IPCLKPORT_CLK, DIV_CLK_MFCMSCL_BUSP, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_MFCMSCL_IN_NORMAL_WORLD
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK, DIV_CLK_MFCMSCL_BUSP, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_RSTnSYNC_CLK_MFCMSCL_MFC_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_ACLK, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
@@ -994,6 +1035,7 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_AS_AXI_M2M_IPCLKPORT_ACLKM, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AS_AXI_M2M_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AS_AXI_M2M_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AS_AXI_M2M_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_MFCMSCL_UID_AS_AXI_M2M_IPCLKPORT_ACLKS, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AS_AXI_M2M_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AS_AXI_M2M_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AS_AXI_M2M_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_GATE(CLK_BLK_MIF_UID_RSTnSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, OSCCLK_MIF, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
@@ -1044,6 +1086,7 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI00_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, OSCCLK_PERI, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_VTS_IN_NORMAL_WORLD
 	CLK_GATE(CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING),
@@ -1059,8 +1102,10 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 	CLK_GATE(GOUT_BLK_VTS_UID_RSTnSYNC_CLK_VTS_BUS_IPCLKPORT_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_VTS_UID_RSTnSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
+#ifdef USE_VTS_IN_NORMAL_WORLD
 	CLK_GATE(GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(CLK_BLK_VTS_UID_u_DMIC_CLK_MUX_IPCLKPORT_D0, DIV_CLK_VTS_DMIC, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_ENABLE_AUTOMATIC_CLKGATING),
@@ -1080,6 +1125,7 @@ struct cmucal_gate cmucal_gate_list[] = {
 	CLK_GATE(GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
 	CLK_GATE(GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
+#endif
 };
 
 /*====================The section of FIXED RATEs===================*/