Add the VME shader for Ivy that supports MVP

This is to optimize the VME parameter for Ivy, which is backported
from Haswell.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

9 files changed, 1393 insertions, 33 deletions

diff --git a/src/gen7_vme.c b/src/gen7_vme.c
index ed8685f..3b1f75e 100644
--- a/src/gen7_vme.c
+++ b/src/gen7_vme.c
@@ -75,11 +75,11 @@ enum MPEG2_VME_KERNEL_TYPE{
 };
  
 static const uint32_t gen7_vme_intra_frame[][4] = {
-#include "shaders/vme/intra_frame.g7b"
+#include "shaders/vme/intra_frame_ivb.g7b"
 };
 
 static const uint32_t gen7_vme_inter_frame[][4] = {
-#include "shaders/vme/inter_frame.g7b"
+#include "shaders/vme/inter_frame_ivb.g7b"
 };
 
 static const uint32_t gen7_vme_batchbuffer[][4] = {
@@ -460,6 +460,12 @@ static VAStatus gen7_vme_vme_state_setup(VADriverContextP ctx,
     return VA_STATUS_SUCCESS;
 }
 
+#define		INTRA_PRED_AVAIL_FLAG_AE	0x60
+#define		INTRA_PRED_AVAIL_FLAG_B		0x10
+#define		INTRA_PRED_AVAIL_FLAG_C       	0x8
+#define		INTRA_PRED_AVAIL_FLAG_D		0x4
+#define		INTRA_PRED_AVAIL_FLAG_BCD_MASK	0x1C
+
 static void
 gen7_vme_fill_vme_batchbuffer(VADriverContextP ctx, 
                               struct encode_state *encode_state,
@@ -469,44 +475,75 @@ gen7_vme_fill_vme_batchbuffer(VADriverContextP ctx,
                               struct intel_encoder_context *encoder_context)
 {
     struct gen6_vme_context *vme_context = encoder_context->vme_context;
-    int number_mb_cmds;
     int mb_x = 0, mb_y = 0;
-    int i, s;
+    int i, s, j;
     unsigned int *command_ptr;
 
+
     dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
     command_ptr = vme_context->vme_batchbuffer.bo->virtual;
 
     for (s = 0; s < encode_state->num_slice_params_ext; s++) {
-        VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; 
-        int slice_mb_begin = pSliceParameter->macroblock_address;
-        int slice_mb_number = pSliceParameter->num_macroblocks;
-        
-        for (i = 0; i < slice_mb_number;  ) {
-            int mb_count = i + slice_mb_begin;    
-            mb_x = mb_count % mb_width;
-            mb_y = mb_count / mb_width;
-            if( i == 0 ) {
-                number_mb_cmds = mb_width;          // we must mark the slice edge. 
-            } else if ( (i + 128 ) <= slice_mb_number) {
-                number_mb_cmds = 128;
-            } else {
-                number_mb_cmds = slice_mb_number - i;
-            }
+        VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
+
+        for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
+            int slice_mb_begin = slice_param->macroblock_address;
+            int slice_mb_number = slice_param->num_macroblocks;
+            unsigned int mb_intra_ub;
+            int slice_mb_x = slice_param->macroblock_address % mb_width;
+
+            for (i = 0; i < slice_mb_number;) {
+                int mb_count = i + slice_mb_begin;    
+
+                mb_x = mb_count % mb_width;
+                mb_y = mb_count / mb_width;
+                mb_intra_ub = 0;
+
+                if (mb_x != 0) {
+                    mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
+                }
+
+                if (mb_y != 0) {
+                    mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
+
+                    if (mb_x != 0)
+                        mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
 
-            *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
-            *command_ptr++ = kernel;
-            *command_ptr++ = 0;
-            *command_ptr++ = 0;
-            *command_ptr++ = 0;
-            *command_ptr++ = 0;
+                    if (mb_x != (mb_width -1))
+                        mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
+                }
+
+                if (i < mb_width) {
+                    if (i == 0)
+                        mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
+
+                    mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
+
+                    if ((i == (mb_width - 1)) && slice_mb_x) {
+                        mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
+                    }
+                }
+		
+                if ((i == mb_width) && slice_mb_x) {
+                    mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
+                }
+
+                *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
+                *command_ptr++ = kernel;
+                *command_ptr++ = 0;
+                *command_ptr++ = 0;
+                *command_ptr++ = 0;
+                *command_ptr++ = 0;
    
-            /*inline data */
-            *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
-            *command_ptr++ = (number_mb_cmds << 16 | transform_8x8_mode_flag | ((i==0) << 1));
+                /*inline data */
+                *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
+                *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
 
-            i += number_mb_cmds;
-        } 
+                i += 1;
+            }
+
+            slice_param++;
+        }
     }
 
     *command_ptr++ = 0;
diff --git a/src/shaders/vme/Makefile.am b/src/shaders/vme/Makefile.am
index cfe8f5f..22b3b00 100644
--- a/src/shaders/vme/Makefile.am
+++ b/src/shaders/vme/Makefile.am
@@ -1,4 +1,5 @@
 VME_CORE	= batchbuffer.asm intra_frame.asm inter_frame.asm
+VME7_CORE	= batchbuffer.asm intra_frame_ivb.asm inter_frame_ivb.asm
 VME75_CORE	= batchbuffer.asm intra_frame_haswell.asm inter_frame_haswell.asm inter_bframe_haswell.asm
 
 INTEL_G6B	= batchbuffer.g6b intra_frame.g6b inter_frame.g6b
@@ -6,9 +7,9 @@ INTEL_G6A	= batchbuffer.g6a intra_frame.g6a inter_frame.g6a
 INTEL_GEN6_INC	= batchbuffer.inc vme.inc
 INTEL_GEN6_ASM	= $(INTEL_G6A:%.g6a=%.gen6.asm)
 
-INTEL_G7B	= batchbuffer.g7b intra_frame.g7b inter_frame.g7b mpeg2_inter_frame.g7b
-INTEL_G7A	= batchbuffer.g7a intra_frame.g7a inter_frame.g7a mpeg2_inter_frame.g7a
-INTEL_GEN7_INC	= batchbuffer.inc vme.inc vme7_mpeg2.inc
+INTEL_G7B	= batchbuffer.g7b intra_frame.g7b inter_frame.g7b mpeg2_inter_frame.g7b intra_frame_ivb.g7b inter_frame_ivb.g7b
+INTEL_G7A	= batchbuffer.g7a intra_frame.g7a inter_frame.g7a mpeg2_inter_frame.g7a intra_frame_ivb.g7a inter_frame_ivb.g7a
+INTEL_GEN7_INC	= batchbuffer.inc vme.inc vme7_mpeg2.inc vme7.inc
 INTEL_GEN7_ASM	= $(INTEL_G7A:%.g7a=%.gen7.asm)
 
 INTEL_G75B	= batchbuffer.g75b intra_frame_haswell.g75b inter_frame_haswell.g75b mpeg2_inter_frame_haswell.g75b inter_bframe_haswell.g75b
diff --git a/src/shaders/vme/inter_frame_ivb.asm b/src/shaders/vme/inter_frame_ivb.asm
new file mode 100644
index 0000000..33af8a5
--- /dev/null
+++ b/src/shaders/vme/inter_frame_ivb.asm
@@ -0,0 +1,568 @@
+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ * Authors: Zhao Yakui <yakui.zhao@intel.com>
+ *
+ */
+// Modual name: InterFrame_ivy.asm
+//
+// Make inter predition estimation for Inter frame on Ivy
+//
+
+//
+//  Now, begin source code....
+//
+
+#define SAVE_RET	add (1) RETURN_REG<1>:ud   ip:ud	32:ud
+#define	RETURN		mov (1)	ip:ud	RETURN_REG<0,1,0>:ud
+
+/*
+ * __START
+ */
+__INTER_START:
+mov  (16) tmp_reg0.0<1>:UD      0x0:UD {align1};
+mov  (16) tmp_reg2.0<1>:UD      0x0:UD {align1};
+mov  (16) tmp_reg4.0<1>:UD      0x0:UD {align1} ;
+mov  (16) tmp_reg6.0<1>:UD      0x0:UD {align1} ;
+
+shl  (2) read0_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
+add  (1) read0_header.0<1>:D    read0_header.0<0,1,0>:D -8:W {align1};     /* X offset */
+add  (1) read0_header.4<1>:D    read0_header.4<0,1,0>:D -1:W {align1};     /* Y offset */ 
+mov  (1) read0_header.8<1>:UD   BLOCK_32X1 {align1};
+mov  (1) read0_header.20<1>:UB  thread_id_ub {align1};                  /* dispatch id */
+
+shl  (2) read1_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
+add  (1) read1_header.0<1>:D    read1_header.0<0,1,0>:D -4:W {align1};     /* X offset */
+mov  (1) read1_header.8<1>:UD   BLOCK_4X16 {align1};
+mov  (1) read1_header.20<1>:UB  thread_id_ub {align1};                  /* dispatch id */
+        
+shl  (2) vme_m0.8<1>:UW         orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
+mov  (1) vme_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
+
+mul  (1) obw_m0.8<1>:UD         w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
+add  (1) obw_m0.8<1>:UD         obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
+mul  (1) obw_m0.8<1>:UD         obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1};
+mov  (1) obw_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
+        
+/*
+ * Media Read Message -- fetch Luma neighbor edge pixels 
+ */
+/* ROW */
+mov  (8) msg_reg0.0<1>:UD       read0_header.0<8,8,1>:UD {align1};        
+send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
+
+/* COL */
+mov  (8) msg_reg0.0<1>:UD       read1_header.0<8,8,1>:UD {align1};                
+send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
+        
+mov  (8) mb_mvp_ref.0<1>:ud	0:ud		{align1};
+mov  (8) mb_ref_win.0<1>:ud	0:ud		{align1};
+and.z.f0.0 (1)		null:uw	mb_hwdep<0,1,0>:uw		0x04:uw   {align1};
+(f0.0) jmpi (1) __mb_hwdep_end;
+/* read back the data for MB A */
+/* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag),
+*  rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID)
+*/
+mov  (8) mba_result.0<1>:ud	0x0:ud		{align1};
+mov  (8) mbb_result.0<1>:ud	0x0:ud		{align1};
+mov  (8) mbc_result.0<1>:ud	0x0:ud		{align1};
+mba_start:
+mov  (8) mb_msg0.0<1>:ud	0:ud		{align1};
+and.z.f0.0 (1)		null:uw	input_mb_intra_ub<0,1,0>:ub	INTRA_PRED_AVAIL_FLAG_AE:uw   {align1};
+/* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */
+(f0.0)  mov  (2)    	mba_result.20<1>:w	-1:w	{align1};
+(f0.0)  jmpi (1)	mbb_start;
+mov  (1) mba_result.0<1>:d	MB_AVAIL		{align1};	
+mov  (2) tmp_reg0.0<1>:UW	orig_xy_ub<2,2,1>:UB	{align1};
+add  (1) tmp_reg0.0<1>:w	tmp_reg0.0<0,1,0>:w	-1:w	{align1};
+mul  (1) mb_msg0.8<1>:UD       w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1};
+add  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD   tmp_reg0.0<0,1,0>:uw {align1};
+mul  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1};
+mov  (1) mb_msg0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
+mov  (1) mb_msg_tmp.8<1>:ud	mb_msg0.8<0,1,0>:ud	{align1};
+
+add  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD      INTER_VME_OUTPUT_MV_IN_OWS:UD {align1};
+/* bind index 3, read 1 oword (16bytes), msg type: 0(OWord Block Read) */
+send (16)
+        mb_ind
+        mb_wb.0<1>:ud
+	NULL
+        data_port(
+                OBR_CACHE_TYPE,
+                OBR_MESSAGE_TYPE,
+                OBR_CONTROL_0,
+                OBR_BIND_IDX,
+                OBR_WRITE_COMMIT_CATEGORY,
+                OBR_HEADER_PRESENT
+        )
+        mlen 1
+        rlen 1
+        {align1};
+
+/* TODO: RefID is required after multi-references are added */
+and.z.f0.0      (1)     null<1>:ud        mb_mode_wb.0<0,1,0>:ud     INTRAMBFLAG_MASK:ud {align1} ;
+(-f0.0)   mov (2)	mba_result.20<1>:w			-1:w	{align1};
+(-f0.0)   jmpi	(1)	mbb_start;
+
+mov   (1) mb_msg0.8<1>:UD	mb_msg_tmp.8<0,1,0>:ud	{align1};
+/* Read MV for MB A */
+/* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */
+send (16)
+        mb_ind
+        mb_mv0.0<1>:ud
+	NULL
+        data_port(
+                OBR_CACHE_TYPE,
+                OBR_MESSAGE_TYPE,
+                OBR_CONTROL_8,
+                OBR_BIND_IDX,
+                OBR_WRITE_COMMIT_CATEGORY,
+                OBR_HEADER_PRESENT
+        )
+        mlen 1
+        rlen 4
+        {align1};
+/* TODO: RefID is required after multi-references are added */
+/* MV */
+mov	   (2)		mba_result.4<1>:ud		mb_mv1.8<2,2,1>:ud	{align1};
+mov	   (1)		mba_result.16<1>:w		MB_PRED_FLAG		{align1};
+
+mbb_start:
+mov  (8) mb_msg0.0<1>:ud	0:ud		{align1};
+and.z.f0.0 (1)		null:uw	input_mb_intra_ub<0,1,0>:ub	INTRA_PRED_AVAIL_FLAG_B:uw   {align1};
+/* MB B doesn't exist. Zero MV. mba_flag is zero */
+/* If MB B doesn't exist, neither MB C nor D exists */
+(f0.0)  mov  (2)    	mbb_result.20<1>:w	-1:w		{align1};
+(f0.0)  mov  (2)    	mbc_result.20<1>:w	-1:w		{align1};
+(f0.0)  jmpi (1)	mb_mvp_start;
+mov  (1) mbb_result.0<1>:d	MB_AVAIL		{align1};	
+mov  (2) tmp_reg0.0<1>:UW	orig_xy_ub<2,2,1>:UB	{align1};
+add  (1) tmp_reg0.2<1>:w	tmp_reg0.2<0,1,0>:w	-1:w	{align1};
+mul  (1) mb_msg0.8<1>:UD       w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1};
+add  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD   tmp_reg0.0<0,1,0>:uw {align1};
+mul  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1};
+mov  (1) mb_msg0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
+mov  (1) mb_msg_tmp.8<1>:ud	mb_msg0.8<0,1,0>:ud	{align1};
+
+add  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD      INTER_VME_OUTPUT_MV_IN_OWS:UD {align1};
+
+/* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */
+send (16)
+        mb_ind
+        mb_wb.0<1>:ud
+	NULL
+        data_port(
+                OBR_CACHE_TYPE,
+                OBR_MESSAGE_TYPE,
+                OBR_CONTROL_0,
+                OBR_BIND_IDX,
+                OBR_WRITE_COMMIT_CATEGORY,
+                OBR_HEADER_PRESENT
+        )
+        mlen 1
+        rlen 1
+        {align1};
+
+/* TODO: RefID is required after multi-references are added */
+and.z.f0.0      (1)     null<1>:ud        mb_mode_wb.0<0,1,0>:ud     INTRAMBFLAG_MASK:ud {align1} ;
+(-f0.0)   mov (2)	mbb_result.20<1>:w			-1:w	{align1};
+(-f0.0)   jmpi	(1)	mbc_start;
+
+mov   (1) mb_msg0.8<1>:UD	mb_msg_tmp.8<0,1,0>:ud	{align1};
+/* Read MV for MB B */
+/* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */
+send (16)
+        mb_ind
+        mb_mv0.0<1>:ud
+	NULL
+        data_port(
+                OBR_CACHE_TYPE,
+                OBR_MESSAGE_TYPE,
+                OBR_CONTROL_8,
+                OBR_BIND_IDX,
+                OBR_WRITE_COMMIT_CATEGORY,
+                OBR_HEADER_PRESENT
+        )
+        mlen 1
+        rlen 4
+        {align1};
+/* TODO: RefID is required after multi-references are added */
+mov	   (2)		mbb_result.4<1>:ud		mb_mv2.16<2,2,1>:ud	{align1};
+mov	   (1)		mbb_result.16<1>:w		MB_PRED_FLAG		{align1};
+
+mbc_start:
+mov  (8) mb_msg0.0<1>:ud	0:ud		{align1};
+and.z.f0.0 (1)		null:uw	input_mb_intra_ub<0,1,0>:ub	INTRA_PRED_AVAIL_FLAG_C:uw   {align1};
+/* MB C doesn't exist. Zero MV. mba_flag is zero */
+/* Based on h264 spec the MB D will be replaced if MB C doesn't exist */
+(f0.0)  jmpi (1)	mbd_start;
+mov  (1) mbc_result.0<1>:d	MB_AVAIL		{align1};	
+mov  (2) tmp_reg0.0<1>:UW	orig_xy_ub<2,2,1>:UB	{align1};
+add  (1) tmp_reg0.2<1>:w	tmp_reg0.2<0,1,0>:w	-1:w	{align1};
+add  (1) tmp_reg0.0<1>:w	tmp_reg0.0<0,1,0>:w	1:w	{align1};
+mul  (1) mb_msg0.8<1>:UD       w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1};
+add  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD   tmp_reg0.0<0,1,0>:uw {align1};
+mul  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1};
+mov  (1) mb_msg0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
+
+mov  (1) mb_msg_tmp.8<1>:ud	mb_msg0.8<0,1,0>:ud	{align1};
+
+add  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD      INTER_VME_OUTPUT_MV_IN_OWS:UD {align1};
+/* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */
+send (16)
+        mb_ind
+        mb_wb.0<1>:ud
+	NULL
+        data_port(
+                OBR_CACHE_TYPE,
+                OBR_MESSAGE_TYPE,
+                OBR_CONTROL_0,
+                OBR_BIND_IDX,
+                OBR_WRITE_COMMIT_CATEGORY,
+                OBR_HEADER_PRESENT
+        )
+        mlen 1
+        rlen 1
+        {align1};
+
+/* TODO: RefID is required after multi-references are added */
+and.z.f0.0      (1)     null<1>:ud        mb_mode_wb.0<0,1,0>:ud     INTRAMBFLAG_MASK:ud {align1} ;
+(-f0.0)   mov (2)	mbc_result.20<1>:w			-1:w	{align1};
+(-f0.0)   jmpi	(1)	mb_mvp_start;
+mov   (1) mb_msg0.8<1>:UD	mb_msg_tmp.8<0,1,0>:ud {align1};
+/* Read MV for MB C */
+/* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */
+send (16)
+        mb_ind
+        mb_mv0.0<1>:ud
+	NULL
+        data_port(
+                OBR_CACHE_TYPE,
+                OBR_MESSAGE_TYPE,
+                OBR_CONTROL_8,
+                OBR_BIND_IDX,
+                OBR_WRITE_COMMIT_CATEGORY,
+                OBR_HEADER_PRESENT
+        )
+        mlen 1
+        rlen 4
+        {align1};
+/* TODO: RefID is required after multi-references are added */
+/* Forward MV */
+mov	   (2)		mbc_result.4<1>:ud		mb_mv2.16<2,2,1>:ud	{align1};
+mov	   (1)		mbc_result.16<1>:w		MB_PRED_FLAG		{align1};
+
+jmpi   (1)    mb_mvp_start;
+mbd_start:
+mov  (1) mbc_result.0<1>:d	MB_AVAIL		{align1};	
+mov  (2) tmp_reg0.0<1>:UW	orig_xy_ub<2,2,1>:UB	{align1};
+add  (2) tmp_reg0.0<1>:w	tmp_reg0.0<2,2,1>:w	-1:w	{align1};
+mul  (1) mb_msg0.8<1>:UD       w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1};
+add  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD   tmp_reg0.0<0,1,0>:uw {align1};
+
+mul  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1};
+mov  (1) mb_msg0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
+mov  (1) mb_msg_tmp.8<1>:ud	mb_msg0.8<0,1,0>:ud	{align1};
+
+add  (1) mb_msg0.8<1>:UD       mb_msg0.8<0,1,0>:UD      INTER_VME_OUTPUT_MV_IN_OWS:UD {align1};
+/* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */
+send (16)
+        mb_ind
+        mb_wb.0<1>:ud
+	NULL
+        data_port(
+                OBR_CACHE_TYPE,
+                OBR_MESSAGE_TYPE,
+                OBR_CONTROL_0,
+                OBR_BIND_IDX,
+                OBR_WRITE_COMMIT_CATEGORY,
+                OBR_HEADER_PRESENT
+        )
+        mlen 1
+        rlen 1
+        {align1};
+
+and.z.f0.0      (1)     null<1>:ud        mb_mode_wb.0<0,1,0>:ud     INTRAMBFLAG_MASK:ud {align1} ;
+(-f0.0)   mov (2)	mbc_result.20<1>:w			-1:w	{align1};
+(-f0.0)   jmpi	(1)	mb_mvp_start;
+
+mov   (1) mb_msg0.8<1>:UD	mb_msg_tmp.8<0,1,0>:ud	{align1};
+/* Read MV for MB D */
+/* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */
+send (16)
+        mb_ind
+        mb_mv0.0<1>:ub
+	NULL
+        data_port(
+                OBR_CACHE_TYPE,
+                OBR_MESSAGE_TYPE,
+                OBR_CONTROL_8,
+                OBR_BIND_IDX,
+                OBR_WRITE_COMMIT_CATEGORY,
+                OBR_HEADER_PRESENT
+        )
+        mlen 1
+        rlen 4
+        {align1};
+
+/* TODO: RefID is required after multi-references are added */
+
+/* Forward MV */
+mov	   (2)		mbc_result.4<1>:ud		mb_mv3.24<2,2,1>:ud	{align1};
+mov	   (1)		mbc_result.16<1>:w		MB_PRED_FLAG		{align1};
+	
+mb_mvp_start:
+/*TODO: Add the skip prediction */
+/* Check whether both MB B and C are invailable */
+add	(1)	tmp_reg0.0<1>:d		mbb_result.0<0,1,0>:d	mbc_result.0<0,1,0>:d	{align1};
+cmp.z.f0.0 (1)	null:d			tmp_reg0.0<0,1,0>:d	0:d	{align1};
+(-f0.0)	jmpi (1)	mb_median_start;
+cmp.nz.f0.0 (1)	null:d	mba_result.0<0,1,0>:d		1:d		{align1};
+(f0.0)	mov	(1)	mbb_result.4<1>:ud		mba_result.4<0,1,0>:ud	{align1};	
+(f0.0)	mov	(1)	mbc_result.4<1>:ud		mba_result.4<0,1,0>:ud	{align1};	
+(f0.0)	mov	(1)	mbb_result.20<1>:uw		mba_result.20<0,1,0>:uw	{align1};	
+(f0.0)	mov	(1)	mbc_result.20<1>:uw		mba_result.20<0,1,0>:uw	{align1};	
+(f0.0)  mov     (1)	mb_mvp_ref.0<1>:ud		mba_result.4<0,1,0>:ud	{align1};
+(-f0.0) mov	(1)	mb_mvp_ref.0<1>:ud		0:ud			{align1};
+jmpi	(1)	__mb_hwdep_end;
+	
+mb_median_start:
+/* check whether only one neighbour MB has the same ref ID with the current MB */
+mov (8)	tmp_reg0.0<1>:ud		0:ud		{align1};
+cmp.z.f0.0	(1)	null:d	mba_result.20<1>:w	0:w	{align1};
+(f0.0)	add	(1)	tmp_reg0.0<1>:w		tmp_reg0.0<1>:w	1:w	{align1};
+(f0.0)	mov	(1)	tmp_reg0.4<1>:ud	mba_result.4<0,1,0>:ud	{align1};
+cmp.z.f0.0	(1)	null:d	mbb_result.20<1>:w	0:w	{align1};
+(f0.0)	add	(1)	tmp_reg0.0<1>:w		tmp_reg0.0<1>:w	1:w	{align1};
+(f0.0)	mov	(1)	tmp_reg0.4<1>:ud	mbb_result.4<0,1,0>:ud	{align1};
+cmp.z.f0.0	(1)	null:d	mbc_result.20<1>:w	0:w	{align1};
+(f0.0)	add	(1)	tmp_reg0.0<1>:w		tmp_reg0.0<1>:w	1:w	{align1};
+(f0.0)	mov	(1)	tmp_reg0.4<1>:ud	mbc_result.4<0,1,0>:ud	{align1};
+cmp.e.f0.0	(1)	null:d	tmp_reg0.0<1>:w	 1:w	{align1};
+(f0.0)	mov	(1)     mb_mvp_ref.0<1>:ud	tmp_reg0.4<0,1,0>:ud	{align1};
+(f0.0)	jmpi (1)  __mb_hwdep_end;
+
+mov	(1)	INPUT_ARG0.0<1>:w	mba_result.4<0,1,0>:w	{align1};
+mov	(1)	INPUT_ARG0.4<1>:w	mbb_result.4<0,1,0>:w	{align1};
+mov	(1)	INPUT_ARG0.8<1>:w	mbc_result.4<0,1,0>:w	{align1};
+SAVE_RET	{align1};
+ jmpi	(1)	word_imedian;
+mov	(1)	mb_mvp_ref.0<1>:w		RET_ARG<0,1,0>:w	{align1};
+mov	(1)	INPUT_ARG0.0<1>:w	mba_result.6<0,1,0>:w	{align1};
+mov	(1)	INPUT_ARG0.4<1>:w	mbb_result.6<0,1,0>:w	{align1};
+mov	(1)	INPUT_ARG0.8<1>:w	mbc_result.6<0,1,0>:w	{align1};
+SAVE_RET	{align1};
+jmpi	(1)	word_imedian; 
+mov	(1)	mb_mvp_ref.2<1>:w		RET_ARG<0,1,0>:w	{align1};
+
+__mb_hwdep_end:
+asr	(2)	mb_ref_win.0<1>:w	mb_mvp_ref.0<2,2,1>:w	2:w	{align1};
+add	(2)	mb_ref_win.8<1>:w	mb_ref_win.0<2,2,1>:w	3:w	{align1};
+and	(2)	mb_ref_win.16<1>:uw	mb_ref_win.8<2,2,1>:uw	0xFFFC:uw {align1};
+
+/* m2 */        
+mov  (8) vme_msg_2<1>:UD        0x0:UD {align1};
+
+/* m3 */
+mov  (1) INEP_ROW.0<1>:UD       0x0:UD {align1};
+and  (1) INEP_ROW.4<1>:UD       INEP_ROW.4<0,1,0>:UD            0xFF000000:UD {align1};
+mov  (8) vme_msg_3<1>:UD        INEP_ROW.0<8,8,1>:UD {align1};        
+
+/* m4 */
+mov  (8) vme_msg_4<1>:UD        0x0 {align1};
+mov (16) vme_msg_4.0<1>:UB      INEP_COL0.3<32,8,4>:UB {align1};
+mov  (1) vme_msg_4.16<1>:UD     INTRA_PREDICTORE_MODE {align1};
+
+
+/* m1 */
+mov  (8) vme_m1.0<1>:ud		0x0:ud	{align1};
+and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1};
+(f0.0) mov  (1) intra_part_mask_ub<1>:UB  LUMA_INTRA_8x8_DISABLE:uw {align1};
+
+/* assign MB intra struct from the thread payload*/
+mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; 
+
+
+/* M0 */
+/* IME search */
+mov  (1) vme_m0.12<1>:UD   SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1};  
+/* 16x16 Source, 1/4 pixel, harr */
+mov  (1) vme_m0.22<1>:UW        REF_REGION_SIZE {align1};         /* Reference Width&Height, 48x40 */
+
+mov  (1) vme_m0.0<1>:UD		vme_m0.8<0,1,0>:UD      {align1};
+
+mov  (1) vme_m0.0<1>:W		-16:W			{align1};
+mov  (1) vme_m0.2<1>:W		-12:W			{align1};
+
+and.z.f0.0 (1)		null:uw	input_mb_intra_ub<0,1,0>:ub	INTRA_PRED_AVAIL_FLAG_AE:uw   {align1};
+(f0.0)	add 	(1)	vme_m0.0<1>:w	vme_m0.0<0,1,0>:w	12:w	{align1};
+and.z.f0.0 (1)		null:uw	input_mb_intra_ub<0,1,0>:ub	INTRA_PRED_AVAIL_FLAG_B:uw   {align1};
+(f0.0)	add 	(1)	vme_m0.2<1>:w	vme_m0.2<0,1,0>:w	8:w	{align1};
+
+mov  (1) vme_m0.4<1>:UD		vme_m0.0<0,1,0>:UD	{align1};
+add  (2) vme_m0.0<1>:w		vme_m0.0<2,2,1>:w	mb_ref_win.16<2,2,1>:w	{align1};
+add  (2) vme_m0.4<1>:w		vme_m0.4<2,2,1>:w	mb_ref_win.16<2,2,1>:w	{align1};
+mov  (8) vme_msg_0.0<1>:UD      vme_m0.0<8,8,1>:UD {align1};
+
+/* m1 */
+
+mov  (1) vme_m1.0<1>:UD         ADAPTIVE_SEARCH_ENABLE:ud {align1} ;
+/* MV num is passed by constant buffer. R4.28 */
+mov  (1) vme_m1.4<1>:UB		r4.28<0,1,0>:UB {align1};
+add  (1) vme_m1.4<1>:UD         vme_m1.4<0,1,0>:UD	FB_PRUNING_DISABLE:UD {align1};
+mov  (1) vme_m1.8<1>:UD         START_CENTER + SEARCH_PATH_LEN:UD {align1};
+
+/* Set the MV cost center */
+mov  (1) vme_m1.16<1>:ud	mb_mvp_ref.0<0,1,0>:ud	{align1};
+mov  (1) vme_m1.20<1>:ud	mb_mvp_ref.0<0,1,0>:ud	{align1};
+mov  (8) vme_msg_1.0<1>:UD      vme_m1.0<8,8,1>:UD {align1};
+
+
+send (8)
+        vme_msg_ind
+        vme_wb
+        null
+        vme(
+                BIND_IDX_VME,
+                0,
+                0,
+                VME_MESSAGE_TYPE_MIXED
+        )
+        mlen vme_msg_length
+        rlen vme_inter_wb_length
+        {align1};
+
+and.z.f0.0      (1)     null<1>:ud              vme_wb0.0<0,1,0>:ud     INTRAMBFLAG_MASK:ud {align1} ;
+
+(-f0.0)jmpi     (1)     __INTRA_INFO ;
+
+__INTER_INFO:
+/* Write MV pairs */	
+mov  (8) msg_reg0.0<1>:UD       obw_m0.0<8,8,1>:UD {align1};
+
+mov  (8) msg_reg1.0<1>:UD       vme_wb1.0<8,8,1>:UD   {align1};
+
+mov  (8) msg_reg2.0<1>:UD       vme_wb2.0<8,8,1>:UD   {align1};
+
+mov  (8) msg_reg3.0<1>:UD       vme_wb3.0<8,8,1>:UD   {align1};
+
+mov  (8) msg_reg4.0<1>:UD       vme_wb4.0<8,8,1>:UD   {align1};                
+/* bind index 3, write  8 oword (128 bytes), msg type: 8(OWord Block Write) */
+send (16)
+        msg_ind
+        obw_wb
+        null
+        data_port(
+                OBW_CACHE_TYPE,
+                OBW_MESSAGE_TYPE,
+                OBW_CONTROL_8,
+                OBW_BIND_IDX,
+                OBW_WRITE_COMMIT_CATEGORY,
+                OBW_HEADER_PRESENT
+        )
+        mlen 5
+        rlen obw_wb_length
+        {align1};
+
+mov             (1)     tmp_uw1<1>:uw           0:uw {align1} ;
+mov             (1)     tmp_ud1<1>:ud           0:ud {align1} ;
+and     	(1)     tmp_uw1<1>:uw           vme_wb0.2<0,1,0>:uw     MV32_BIT_MASK:uw {align1} ;
+shr       	(1)     tmp_uw1<1>:uw           tmp_uw1<1>:uw           MV32_BIT_SHIFT:uw {align1} ;
+mul       	(1)     tmp_ud1<1>:ud           tmp_uw1<0,1,0>:uw       96:uw {align1} ;
+add       	(1)     tmp_ud1<1>:ud           tmp_ud1<0,1,0>:ud       32:uw {align1} ;
+shl       (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       MFC_MV32_BIT_SHIFT:uw {align1} ;
+add       (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       MVSIZE_UW_BASE:uw {align1} ;
+add             (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       CBP_DC_YUV_UW:uw {align1} ;
+
+mov             (1)     msg_reg1.0<1>:uw        vme_wb0.0<0,1,0>:uw     {align1} ;
+mov             (1)     msg_reg1.2<1>:uw        tmp_uw1<0,1,0>:uw       {align1} ;
+mov             (1)     msg_reg1.4<1>:UD        vme_wb0.28<0,1,0>:UD    {align1};
+mov             (1)     msg_reg1.8<1>:ud        tmp_ud1<0,1,0>:ud       {align1} ;
+mov             (1)     msg_reg1.12<1>:ud        vme_wb0.0<0,1,0>:ud     {align1} ;
+mov             (1)     msg_reg1.16<1>:ud        0x25:ud     {align1} ;
+jmpi		(1) 	__OUTPUT_INFO;
+
+__INTRA_INFO:
+mov             (1)     msg_reg1.0<1>:UD        vme_wb.0<0,1,0>:UD      {align1};
+mov             (1)     msg_reg1.4<1>:UD        vme_wb.16<0,1,0>:UD     {align1};
+mov             (1)     msg_reg1.8<1>:UD        vme_wb.20<0,1,0>:UD     {align1};
+mov             (1)     msg_reg1.12<1>:UD       vme_wb.24<0,1,0>:UD     {align1};
+mov             (1)     msg_reg1.16<1>:ud        0x35:ud     {align1} ;
+
+__OUTPUT_INFO:
+
+mov	(1)	msg_reg1.20<1>:ud	obw_m0.8<0,1,0>:ud	{align1};
+add     (1)     obw_m0.8<1>:UD       obw_m0.8<0,1,0>:UD      INTER_VME_OUTPUT_MV_IN_OWS:UD {align1};
+mov	(8)	msg_reg0.0<1>:ud	obw_m0.0<8,8,1>:ud	{align1};
+
+
+/* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */
+send (16)
+        msg_ind
+        obw_wb
+        null
+        data_port(
+                OBW_CACHE_TYPE,
+                OBW_MESSAGE_TYPE,
+                OBW_CONTROL_2,
+                OBW_BIND_IDX,
+                OBW_WRITE_COMMIT_CATEGORY,
+                OBW_HEADER_PRESENT
+        )
+        mlen 2
+        rlen obw_wb_length
+        {align1};
+
+__EXIT: 
+/*
+ * kill thread
+ */        
+mov  (8) ts_msg_reg0<1>:UD         r0<8,8,1>:UD {align1};
+send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
+
+
+	nop		;
+	nop		;
+/* Compare three word data to get the min value */
+word_imin:
+	cmp.le.f0.0 (1)		null:w		INPUT_ARG0.0<0,1,0>:w	INPUT_ARG0.4<0,1,0>:w {align1};
+	(f0.0) mov  (1)		TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w			  {align1};
+	(-f0.0) mov (1)		TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w			  {align1};
+	cmp.le.f0.0 (1)		null:w		TEMP_VAR0.0<0,1,0>:w	INPUT_ARG0.8<0,1,0>:w {align1};
+	(f0.0) mov  (1)		RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w			  {align1};
+	(-f0.0) mov (1)		RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w			  {align1};
+	RETURN		{align1};	
+	
+/* Compare three word data to get the max value */
+word_imax:
+	cmp.ge.f0.0 (1)		null:w		INPUT_ARG0.0<0,1,0>:w	INPUT_ARG0.4<0,1,0>:w {align1};
+	(f0.0) mov  (1)		TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w			  {align1};
+	(-f0.0) mov (1)		TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w			  {align1};
+	cmp.ge.f0.0 (1)		null:w		TEMP_VAR0.0<0,1,0>:w	INPUT_ARG0.8<0,1,0>:w {align1};
+	(f0.0) mov  (1)		RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w			  {align1};
+	(-f0.0) mov (1)		RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w			  {align1};
+	RETURN		{align1};	
+	
+word_imedian:
+	cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1};
+	(f0.0)	jmpi (1) cmp_a_ge_b;
+	cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1};
+	(f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1};
+	(f0.0) jmpi (1) cmp_end;
+	cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1};
+	(f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1};
+	(-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1};
+	jmpi (1) cmp_end;
+cmp_a_ge_b:
+	cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1};
+	(f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1};
+	(f0.0) jmpi (1) cmp_end;
+	cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1};
+	(f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1};
+	(-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1};
+cmp_end:
+ 	RETURN	{align1};
+
diff --git a/src/shaders/vme/inter_frame_ivb.g7a b/src/shaders/vme/inter_frame_ivb.g7a
new file mode 100644
index 0000000..77293ee
--- /dev/null
+++ b/src/shaders/vme/inter_frame_ivb.g7a
@@ -0,0 +1,2 @@
+#include "vme7.inc"
+#include "inter_frame_ivb.asm"
diff --git a/src/shaders/vme/inter_frame_ivb.g7b b/src/shaders/vme/inter_frame_ivb.g7b
new file mode 100644
index 0000000..bfe3e5a
--- /dev/null
+++ b/src/shaders/vme/inter_frame_ivb.g7b
@@ -0,0 +1,250 @@
+   { 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24800061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 },
+   { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 },
+   { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 },
+   { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff },
+   { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f },
+   { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
+   { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 },
+   { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc },
+   { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 },
+   { 0x00000001, 0x24340231, 0x00000014, 0x00000000 },
+   { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 },
+   { 0x00000001, 0x24540231, 0x00000014, 0x00000000 },
+   { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 },
+   { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 },
+   { 0x00000041, 0x24880c21, 0x00000488, 0x0000000a },
+   { 0x00000001, 0x24940231, 0x00000014, 0x00000000 },
+   { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
+   { 0x04600031, 0x23801cb1, 0x00000800, 0x02190004 },
+   { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 },
+   { 0x04600031, 0x23a01cb1, 0x00000800, 0x02290004 },
+   { 0x00600001, 0x2ac00061, 0x00000000, 0x00000000 },
+   { 0x00600001, 0x2a800061, 0x00000000, 0x00000000 },
+   { 0x01000005, 0x20002d28, 0x000000a6, 0x00040004 },
+   { 0x00010020, 0x34001c00, 0x00001400, 0x000000f2 },
+   { 0x00600001, 0x2ae00061, 0x00000000, 0x00000000 },
+   { 0x00600001, 0x2b000061, 0x00000000, 0x00000000 },
+   { 0x00600001, 0x2b200061, 0x00000000, 0x00000000 },
+   { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 },
+   { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 },
+   { 0x00210001, 0x2af401ed, 0x00000000, 0xffffffff },
+   { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 },
+   { 0x00000001, 0x2ae000e5, 0x00000000, 0x00000001 },
+   { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 },
+   { 0x00000040, 0x24003dad, 0x00000400, 0xffffffff },
+   { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 },
+   { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 },
+   { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a },
+   { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 },
+   { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 },
+   { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 },
+   { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 },
+   { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 },
+   { 0x00310001, 0x2af401ed, 0x00000000, 0xffffffff },
+   { 0x00110020, 0x34001c00, 0x00001400, 0x00000008 },
+   { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 },
+   { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 },
+   { 0x00200001, 0x2ae40021, 0x00450bc8, 0x00000000 },
+   { 0x00000001, 0x2af001ed, 0x00000000, 0x00010001 },
+   { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 },
+   { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 },
+   { 0x00210001, 0x2b1401ed, 0x00000000, 0xffffffff },
+   { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff },
+   { 0x00010020, 0x34001c00, 0x00001400, 0x00000070 },
+   { 0x00000001, 0x2b0000e5, 0x00000000, 0x00000001 },
+   { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 },
+   { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff },
+   { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 },
+   { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 },
+   { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a },
+   { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 },
+   { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 },
+   { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 },
+   { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 },
+   { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 },
+   { 0x00310001, 0x2b1401ed, 0x00000000, 0xffffffff },
+   { 0x00110020, 0x34001c00, 0x00001400, 0x00000008 },
+   { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 },
+   { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 },
+   { 0x00200001, 0x2b040021, 0x00450bf0, 0x00000000 },
+   { 0x00000001, 0x2b1001ed, 0x00000000, 0x00010001 },
+   { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 },
+   { 0x01000005, 0x20002e28, 0x000000a5, 0x00080008 },
+   { 0x00010020, 0x34001c00, 0x00001400, 0x00000026 },
+   { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 },
+   { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 },
+   { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff },
+   { 0x00000040, 0x24003dad, 0x00000400, 0x00010001 },
+   { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 },
+   { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 },
+   { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a },
+   { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 },
+   { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 },
+   { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 },
+   { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 },
+   { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 },
+   { 0x00310001, 0x2b3401ed, 0x00000000, 0xffffffff },
+   { 0x00110020, 0x34001c00, 0x00001400, 0x0000002c },
+   { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 },
+   { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 },
+   { 0x00200001, 0x2b240021, 0x00450bf0, 0x00000000 },
+   { 0x00000001, 0x2b3001ed, 0x00000000, 0x00010001 },
+   { 0x00000020, 0x34001c00, 0x00001400, 0x00000022 },
+   { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 },
+   { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 },
+   { 0x00200040, 0x24003dad, 0x00450400, 0xffffffff },
+   { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 },
+   { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 },
+   { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a },
+   { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 },
+   { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 },
+   { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 },
+   { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 },
+   { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 },
+   { 0x00310001, 0x2b3401ed, 0x00000000, 0xffffffff },
+   { 0x00110020, 0x34001c00, 0x00001400, 0x00000008 },
+   { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 },
+   { 0x0a800031, 0x2ba01cb1, 0x00000b40, 0x02480403 },
+   { 0x00200001, 0x2b240021, 0x00450c18, 0x00000000 },
+   { 0x00000001, 0x2b3001ed, 0x00000000, 0x00010001 },
+   { 0x00000040, 0x240014a5, 0x00000b00, 0x00000b20 },
+   { 0x01000010, 0x20001ca4, 0x00000400, 0x00000000 },
+   { 0x00110020, 0x34001c00, 0x00001400, 0x00000010 },
+   { 0x02000010, 0x20001ca4, 0x00000ae0, 0x00000001 },
+   { 0x00010001, 0x2b040021, 0x00000ae4, 0x00000000 },
+   { 0x00010001, 0x2b240021, 0x00000ae4, 0x00000000 },
+   { 0x00010001, 0x2b140129, 0x00000af4, 0x00000000 },
+   { 0x00010001, 0x2b340129, 0x00000af4, 0x00000000 },
+   { 0x00010001, 0x2ac00021, 0x00000ae4, 0x00000000 },
+   { 0x00110001, 0x2ac00061, 0x00000000, 0x00000000 },
+   { 0x00000020, 0x34001c00, 0x00001400, 0x00000032 },
+   { 0x00600001, 0x24000061, 0x00000000, 0x00000000 },
+   { 0x01000010, 0x20003da4, 0x00200af4, 0x00000000 },
+   { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 },
+   { 0x00010001, 0x24040021, 0x00000ae4, 0x00000000 },
+   { 0x01000010, 0x20003da4, 0x00200b14, 0x00000000 },
+   { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 },
+   { 0x00010001, 0x24040021, 0x00000b04, 0x00000000 },
+   { 0x01000010, 0x20003da4, 0x00200b34, 0x00000000 },
+   { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 },
+   { 0x00010001, 0x24040021, 0x00000b24, 0x00000000 },
+   { 0x01000010, 0x20003da4, 0x00200400, 0x00010001 },
+   { 0x00010001, 0x2ac00021, 0x00000404, 0x00000000 },
+   { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 },
+   { 0x00000001, 0x2fa001ad, 0x00000ae4, 0x00000000 },
+   { 0x00000001, 0x2fa401ad, 0x00000b04, 0x00000000 },
+   { 0x00000001, 0x2fa801ad, 0x00000b24, 0x00000000 },
+   { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 },
+   { 0x00000020, 0x34001c00, 0x00001400, 0x000000ba },
+   { 0x00000001, 0x2ac001ad, 0x00000fe4, 0x00000000 },
+   { 0x00000001, 0x2fa001ad, 0x00000ae6, 0x00000000 },
+   { 0x00000001, 0x2fa401ad, 0x00000b06, 0x00000000 },
+   { 0x00000001, 0x2fa801ad, 0x00000b26, 0x00000000 },
+   { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 },
+   { 0x00000020, 0x34001c00, 0x00001400, 0x000000ae },
+   { 0x00000001, 0x2ac201ad, 0x00000fe4, 0x00000000 },
+   { 0x0020000c, 0x2a803dad, 0x00450ac0, 0x00020002 },
+   { 0x00200040, 0x2a883dad, 0x00450a80, 0x00030003 },
+   { 0x00200005, 0x2a902d29, 0x00450a88, 0xfffcfffc },
+   { 0x00600001, 0x28400061, 0x00000000, 0x00000000 },
+   { 0x00000001, 0x23800061, 0x00000000, 0x00000000 },
+   { 0x00000005, 0x23840c21, 0x00000384, 0xff000000 },
+   { 0x00600001, 0x28600021, 0x008d0380, 0x00000000 },
+   { 0x00600001, 0x288000e1, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x28800231, 0x00cf03a3, 0x00000000 },
+   { 0x00000001, 0x28900061, 0x00000000, 0x11111111 },
+   { 0x00600001, 0x24600061, 0x00000000, 0x00000000 },
+   { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 },
+   { 0x00010001, 0x247c0171, 0x00000000, 0x00020002 },
+   { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 },
+   { 0x00000001, 0x244c0061, 0x00000000, 0x00203000 },
+   { 0x00000001, 0x24560169, 0x00000000, 0x28302830 },
+   { 0x00000001, 0x24400021, 0x00000448, 0x00000000 },
+   { 0x00000001, 0x244001ed, 0x00000000, 0xfff0fff0 },
+   { 0x00000001, 0x244201ed, 0x00000000, 0xfff4fff4 },
+   { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 },
+   { 0x00010040, 0x24403dad, 0x00000440, 0x000c000c },
+   { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 },
+   { 0x00010040, 0x24423dad, 0x00000442, 0x00080008 },
+   { 0x00000001, 0x24440021, 0x00000440, 0x00000000 },
+   { 0x00200040, 0x244035ad, 0x00450440, 0x00450a90 },
+   { 0x00200040, 0x244435ad, 0x00450444, 0x00450a90 },
+   { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 },
+   { 0x00000001, 0x24600061, 0x00000000, 0x00000002 },
+   { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 },
+   { 0x00000040, 0x24640c21, 0x00000464, 0x00000000 },
+   { 0x00000001, 0x24680061, 0x00000000, 0x30003030 },
+   { 0x00000001, 0x24700021, 0x00000ac0, 0x00000000 },
+   { 0x00000001, 0x24740021, 0x00000ac0, 0x00000000 },
+   { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 },
+   { 0x08600031, 0x21801cbd, 0x00000800, 0x0a686000 },
+   { 0x01000005, 0x20000c20, 0x00000180, 0x00002000 },
+   { 0x00110020, 0x34001c00, 0x00001400, 0x0000002c },
+   { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+   { 0x00600001, 0x28200021, 0x008d01a0, 0x00000000 },
+   { 0x00600001, 0x28400021, 0x008d01c0, 0x00000000 },
+   { 0x00600001, 0x28600021, 0x008d01e0, 0x00000000 },
+   { 0x00600001, 0x28800021, 0x008d0200, 0x00000000 },
+   { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 },
+   { 0x00000001, 0x25420169, 0x00000000, 0x00000000 },
+   { 0x00000001, 0x25440061, 0x00000000, 0x00000000 },
+   { 0x00000005, 0x25422d29, 0x00000182, 0x00200020 },
+   { 0x00000008, 0x25422d29, 0x00200542, 0x00050005 },
+   { 0x00000041, 0x25442d21, 0x00000542, 0x00600060 },
+   { 0x00000040, 0x25442c21, 0x00000544, 0x00200020 },
+   { 0x00000009, 0x25422d29, 0x00000542, 0x00050005 },
+   { 0x00000040, 0x25422d29, 0x00000542, 0x00400040 },
+   { 0x00000040, 0x25422d29, 0x00000542, 0x000e000e },
+   { 0x00000001, 0x28200129, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x28220129, 0x00000542, 0x00000000 },
+   { 0x00000001, 0x28240021, 0x0000019c, 0x00000000 },
+   { 0x00000001, 0x28280021, 0x00000544, 0x00000000 },
+   { 0x00000001, 0x282c0021, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x28300061, 0x00000000, 0x00000025 },
+   { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a },
+   { 0x00000001, 0x28200021, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x28240021, 0x00000190, 0x00000000 },
+   { 0x00000001, 0x28280021, 0x00000194, 0x00000000 },
+   { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 },
+   { 0x00000001, 0x28300061, 0x00000000, 0x00000035 },
+   { 0x00000001, 0x28340021, 0x00000488, 0x00000000 },
+   { 0x00000040, 0x24880c21, 0x00000488, 0x00000008 },
+   { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+   { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 },
+   { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 },
+   { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x06000010, 0x200035ac, 0x00000fa0, 0x00000fa4 },
+   { 0x00010001, 0x2f6001ad, 0x00000fa0, 0x00000000 },
+   { 0x00110001, 0x2f6001ad, 0x00000fa4, 0x00000000 },
+   { 0x06000010, 0x200035ac, 0x00000f60, 0x00000fa8 },
+   { 0x00010001, 0x2fe401ad, 0x00000f60, 0x00000000 },
+   { 0x00110001, 0x2fe401ad, 0x00000fa8, 0x00000000 },
+   { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 },
+   { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 },
+   { 0x00010001, 0x2f6001ad, 0x00000fa0, 0x00000000 },
+   { 0x00110001, 0x2f6001ad, 0x00000fa4, 0x00000000 },
+   { 0x04000010, 0x200035ac, 0x00000f60, 0x00000fa8 },
+   { 0x00010001, 0x2fe401ad, 0x00000f60, 0x00000000 },
+   { 0x00110001, 0x2fe401ad, 0x00000fa8, 0x00000000 },
+   { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 },
+   { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 },
+   { 0x00010020, 0x34001c00, 0x00001400, 0x0000000e },
+   { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 },
+   { 0x00010001, 0x2fe401ad, 0x00000fa0, 0x00000000 },
+   { 0x00010020, 0x34001c00, 0x00001400, 0x00000014 },
+   { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 },
+   { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 },
+   { 0x00110001, 0x2fe401ad, 0x00000fa4, 0x00000000 },
+   { 0x00000020, 0x34001c00, 0x00001400, 0x0000000c },
+   { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 },
+   { 0x00010001, 0x2fe401ad, 0x00000fa4, 0x00000000 },
+   { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 },
+   { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 },
+   { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 },
+   { 0x00110001, 0x2fe401ad, 0x00000fa0, 0x00000000 },
+   { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 },
diff --git a/src/shaders/vme/intra_frame_ivb.asm b/src/shaders/vme/intra_frame_ivb.asm
new file mode 100644
index 0000000..321cc0c
--- /dev/null
+++ b/src/shaders/vme/intra_frame_ivb.asm
@@ -0,0 +1,138 @@
+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+// Modual name: IntraFrame.asm
+//
+// Make intra predition estimation for Intra frame
+//
+
+//
+//  Now, begin source code....
+//
+
+/*
+ * __START
+ */
+__INTRA_START:
+mov  (16) tmp_reg0.0<1>:UD      0x0:UD {align1};
+mov  (16) tmp_reg2.0<1>:UD      0x0:UD {align1};
+mov  (16) tmp_reg4.0<1>:UD      0x0:UD {align1} ;
+mov  (16) tmp_reg6.0<1>:UD      0x0:UD {align1} ;
+
+shl  (2) read0_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
+add  (1) read0_header.0<1>:D    read0_header.0<0,1,0>:D -8:W {align1};     /* X offset */
+add  (1) read0_header.4<1>:D    read0_header.4<0,1,0>:D -1:W {align1};     /* Y offset */ 
+mov  (1) read0_header.8<1>:UD   BLOCK_32X1 {align1};
+mov  (1) read0_header.20<1>:UB  thread_id_ub {align1};                  /* dispatch id */
+
+shl  (2) read1_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
+add  (1) read1_header.0<1>:D    read1_header.0<0,1,0>:D -4:W {align1};     /* X offset */
+mov  (1) read1_header.8<1>:UD   BLOCK_4X16 {align1};
+mov  (1) read1_header.20<1>:UB  thread_id_ub {align1};                  /* dispatch id */
+        
+shl  (2) vme_m0.8<1>:UW         orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
+mov  (1) vme_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
+
+mul  (1) obw_m0.8<1>:UD         w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
+add  (1) obw_m0.8<1>:UD         obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
+mov  (1) obw_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
+        
+/*
+ * Media Read Message -- fetch Luma neighbor edge pixels 
+ */
+/* ROW */
+mov  (8) msg_reg0.0<1>:UD       read0_header.0<8,8,1>:UD {align1};        
+send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
+
+/* COL */
+mov  (8) msg_reg0.0<1>:UD       read1_header.0<8,8,1>:UD {align1};                
+send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
+        
+/* m0 */        
+mov  (8) vme_msg_0.0<1>:UD      vme_m0.0<8,8,1>:UD {align1};
+
+/* m2 */        
+mov  (8) vme_msg_2<1>:UD        0x0:UD {align1};
+
+/*
+ * VME message
+ */
+/* m0 */        
+mov  (8) vme_msg_0.0<1>:UD      vme_m0.0<8,8,1>:UD {align1};
+
+/* m1 */
+mov  (8) vme_m1.0<1>:ud		0x0:ud	{align1};
+and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1};
+(f0.0) mov  (1) intra_part_mask_ub<1>:UB  LUMA_INTRA_8x8_DISABLE:uw {align1};
+
+/* assign MB intra struct from the thread payload*/
+mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; 
+                           
+mov  (8) vme_msg_1<1>:UD        vme_m1.0<8,8,1>:UD {align1};
+
+/* m2 */        
+mov (8) vme_msg_2<1>:UD         0x0:UD {align1};
+
+/* m3 */
+mov  (1) INEP_ROW.0<1>:UD       0x0:UD {align1};
+and  (1) INEP_ROW.4<1>:UD       INEP_ROW.4<0,1,0>:UD            0xFF000000:UD {align1};
+mov  (8) vme_msg_3<1>:UD         INEP_ROW.0<8,8,1>:UD {align1};
+
+/* m4 */        
+mov  (8) vme_msg_4<1>:UD         0x0 {align1};
+mov (16) vme_msg_4.0<1>:UB       INEP_COL0.3<32,8,4>:UB {align1};
+mov  (1) vme_msg_4.16<1>:UD      INTRA_PREDICTORE_MODE {align1};
+
+send (8)
+        vme_msg_ind
+        vme_wb
+        null
+        vme(
+                BIND_IDX_VME,
+                0,
+                0,
+                VME_MESSAGE_TYPE_INTRA
+        )
+        mlen vme_msg_length
+        rlen vme_intra_wb_length
+        {align1};
+
+
+/*
+ * Oword Block Write message
+ */
+mov  (8) msg_reg0.0<1>:UD       obw_m0<8,8,1>:UD {align1};
+        
+mov  (1) msg_reg1.0<1>:UD       vme_wb.0<0,1,0>:UD      {align1};
+mov  (1) msg_reg1.4<1>:UD       vme_wb.16<0,1,0>:UD     {align1};
+mov  (1) msg_reg1.8<1>:UD       vme_wb.20<0,1,0>:UD     {align1};
+mov  (1) msg_reg1.12<1>:UD      vme_wb.24<0,1,0>:UD     {align1};
+
+/* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */
+send (16)
+        msg_ind
+        obw_wb
+        null
+        data_port(
+                OBW_CACHE_TYPE,
+                OBW_MESSAGE_TYPE,
+                OBW_CONTROL_0,
+                OBW_BIND_IDX,
+                OBW_WRITE_COMMIT_CATEGORY,
+                OBW_HEADER_PRESENT
+        )
+        mlen 2
+        rlen obw_wb_length
+        {align1};
+
+__EXIT: 
+/*
+ * kill thread
+ */        
+mov  (8) ts_msg_reg0<1>:UD         r0<8,8,1>:UD {align1};
+send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
diff --git a/src/shaders/vme/intra_frame_ivb.g7a b/src/shaders/vme/intra_frame_ivb.g7a
new file mode 100644
index 0000000..a1b195a
--- /dev/null
+++ b/src/shaders/vme/intra_frame_ivb.g7a
@@ -0,0 +1,3 @@
+#include "vme7.inc"
+#include "intra_frame_ivb.asm"
+
diff --git a/src/shaders/vme/intra_frame_ivb.g7b b/src/shaders/vme/intra_frame_ivb.g7b
new file mode 100644
index 0000000..748cfdf
--- /dev/null
+++ b/src/shaders/vme/intra_frame_ivb.g7b
@@ -0,0 +1,46 @@
+   { 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24800061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 },
+   { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 },
+   { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 },
+   { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff },
+   { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f },
+   { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
+   { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 },
+   { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc },
+   { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 },
+   { 0x00000001, 0x24340231, 0x00000014, 0x00000000 },
+   { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 },
+   { 0x00000001, 0x24540231, 0x00000014, 0x00000000 },
+   { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 },
+   { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 },
+   { 0x00000001, 0x24940231, 0x00000014, 0x00000000 },
+   { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
+   { 0x04600031, 0x23801cb1, 0x00000800, 0x02190004 },
+   { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 },
+   { 0x04600031, 0x23a01cb1, 0x00000800, 0x02290004 },
+   { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 },
+   { 0x00600001, 0x28400061, 0x00000000, 0x00000000 },
+   { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 },
+   { 0x00600001, 0x24600061, 0x00000000, 0x00000000 },
+   { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 },
+   { 0x00010001, 0x247c0171, 0x00000000, 0x00020002 },
+   { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 },
+   { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 },
+   { 0x00600001, 0x28400061, 0x00000000, 0x00000000 },
+   { 0x00000001, 0x23800061, 0x00000000, 0x00000000 },
+   { 0x00000005, 0x23840c21, 0x00000384, 0xff000000 },
+   { 0x00600001, 0x28600021, 0x008d0380, 0x00000000 },
+   { 0x00600001, 0x288000e1, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x28800231, 0x00cf03a3, 0x00000000 },
+   { 0x00000001, 0x28900061, 0x00000000, 0x11111111 },
+   { 0x08600031, 0x21801cbd, 0x00000800, 0x0a184000 },
+   { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+   { 0x00000001, 0x28200021, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x28240021, 0x00000190, 0x00000000 },
+   { 0x00000001, 0x28280021, 0x00000194, 0x00000000 },
+   { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 },
+   { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 },
+   { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 },
+   { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 },
diff --git a/src/shaders/vme/vme7.inc b/src/shaders/vme/vme7.inc
new file mode 100644
index 0000000..952847e
--- /dev/null
+++ b/src/shaders/vme/vme7.inc
@@ -0,0 +1,315 @@
+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+// Modual name: ME_header.inc
+//
+// Global symbols define
+//
+
+/*
+ * Constant
+ */
+define(`VME_MESSAGE_TYPE_INTER',        `1')
+define(`VME_MESSAGE_TYPE_INTRA',        `2')
+define(`VME_MESSAGE_TYPE_MIXED',        `3')
+        
+define(`BLOCK_32X1',                    `0x0000001F')
+define(`BLOCK_4X16',                    `0x000F0003')
+        
+define(`LUMA_INTRA_16x16_DISABLE',      `0x1')
+define(`LUMA_INTRA_8x8_DISABLE',        `0x2')
+define(`LUMA_INTRA_4x4_DISABLE',        `0x4')
+
+define(`INTRA_PRED_AVAIL_FLAG_AE',      `0x60')
+define(`INTRA_PRED_AVAIL_FLAG_B',       `0x10')
+define(`INTRA_PRED_AVAIL_FLAG_C',       `0x8')
+define(`INTRA_PRED_AVAIL_FLAG_D',       `0x4')
+
+define(`BIND_IDX_VME',                  `0')
+define(`BIND_IDX_VME_REF0',             `1')
+define(`BIND_IDX_VME_REF1',             `2')
+define(`BIND_IDX_OUTPUT',               `3')
+define(`BIND_IDX_INEP',                 `4')
+
+define(`SUB_PEL_MODE_INTEGER',          `0x00000000')
+define(`SUB_PEL_MODE_HALF',             `0x00001000')
+define(`SUB_PEL_MODE_QUARTER',          `0x00003000')
+
+define(`INTER_SAD_NONE',                `0x00000000')
+define(`INTER_SAD_HAAR',                `0x00200000')
+
+define(`INTRA_SAD_NONE',                `0x00000000')
+define(`INTRA_SAD_HAAR',                `0x00800000')
+
+define(`INTER_PART_MASK',               `0x00000000')
+
+define(`SEARCH_CTRL_SINGLE',            `0x00000000')
+define(`SEARCH_CTRL_DUAL_START',        `0x00000100')
+define(`SEARCH_CTRL_DUAL_RECORD',       `0x00000300')
+define(`SEARCH_CTRL_DUAL_REFERENCE',    `0x00000700')
+
+define(`REF_REGION_SIZE',               `0x2830:UW')
+
+define(`BI_SUB_MB_PART_MASK',           `0x0c000000')
+define(`MAX_NUM_MV',                    `0x00000020')
+define(`FB_PRUNING_ENABLE',             `0x40000000')
+define(`FB_PRUNING_DISABLE',             `0x00000000')
+
+define(`SEARCH_PATH_LEN',               `0x00003030')
+define(`START_CENTER',                  `0x30000000')
+
+define(`ADAPTIVE_SEARCH_ENABLE',        `0x00000002') 
+define(`INTRA_PREDICTORE_MODE',         `0x11111111:UD')
+
+define(`INTER_VME_OUTPUT_IN_OWS',       `10')
+define(`INTER_VME_OUTPUT_MV_IN_OWS',    `8')
+
+define(`INTRAMBFLAG_MASK',              `0x00002000')
+define(`MVSIZE_UW_BASE',                `0x0040')
+define(`MFC_MV32_BIT_SHIFT',            `5')
+define(`CBP_DC_YUV_UW',                 `0x000E')
+
+define(`DC_HARR_ENABLE',                `0x0000')
+define(`DC_HARR_DISABLE',		`0x0020')
+
+define(`MV32_BIT_MASK',                 `0x0020')
+define(`MV32_BIT_SHIFT',                `5')
+
+define(`OBW_CACHE_TYPE',                `10')
+
+
+define(`OBW_MESSAGE_TYPE',              `8')
+
+define(`OBW_BIND_IDX',                  `BIND_IDX_OUTPUT')
+
+define(`OBW_CONTROL_0',                 `0')    /* 1 OWord, low 128 bits */
+define(`OBW_CONTROL_1',                 `1')    /* 1 OWord, high 128 bits */
+define(`OBW_CONTROL_2',                 `2')    /* 2 OWords */
+define(`OBW_CONTROL_3',                 `3')    /* 4 OWords */
+define(`OBW_CONTROL_8',                 `4')    /* 8 OWords */
+
+define(`FME_REPART_ENABLE',		`0x80000000')
+define(`FME_REPART_DISABLE',		`0x00000000')
+define(`FME_SINGLE_PARTION',		`0x00000000')
+define(`FME_MUL_PARTION',		`0x00000008')
+
+
+define(`OBW_WRITE_COMMIT_CATEGORY',     `0')    /* category on Ivybridge */
+
+
+define(`OBW_HEADER_PRESENT',            `1')
+
+/* GRF registers
+ * r0 header
+ * r1~r4 constant buffer (reserved)
+ * r5 inline data
+ * r6~r11 reserved        
+ * r12 write back of VME message
+ * r13 write back of Oword Block Write        
+ */
+/*
+ * GRF 0 -- header       
+ */        
+define(`thread_id_ub',          `r0.20<0,1,0>:UB')  /* thread id in payload */
+
+/*
+ * GRF 1~4 -- Constant Buffer (reserved)
+ */
+        
+/*
+ * GRF 5 -- inline data
+ */        
+define(`inline_reg0',           `r5')
+define(`w_in_mb_uw',            `inline_reg0.2')
+define(`orig_xy_ub',            `inline_reg0.0')
+define(`orig_x_ub',             `inline_reg0.0')    /* in macroblock */    
+define(`orig_y_ub',             `inline_reg0.1')
+define(`transform_8x8_ub',      `inline_reg0.4')
+define(`input_mb_intra_ub',     `inline_reg0.5')
+define(`num_macroblocks',       `inline_reg0.6')
+
+/*
+ * GRF 6~11 -- reserved
+ */
+
+/*
+ * GRF 12~15 -- write back for VME message 
+ */
+define(`vme_wb',                `r12')
+define(`vme_wb0',               `r12')
+define(`vme_wb1',               `r13')
+define(`vme_wb2',               `r14')
+define(`vme_wb3',               `r15')
+define(`vme_wb4',               `r16')
+define(`vme_wb5',               `r17')
+define(`vme_wb6',               `r18')
+
+
+/*
+ * GRF 24 -- write for VME output message
+ */
+define(`obw_wb',                `null<1>:W')
+define(`obw_wb_length',         `0')
+
+
+/*
+ * GRF 28~30 -- Intra Neighbor Edge Pixels
+ */
+define(`INEP_ROW',              `r28')
+define(`INEP_COL0',             `r29')
+define(`INEP_COL1',             `r30')
+        
+/*
+ * temporary registers
+ */
+define(`tmp_reg0',              `r32')
+define(`read0_header',          `tmp_reg0')
+define(`tmp_reg1',              `r33')
+define(`read1_header',          `tmp_reg1')
+define(`tmp_reg2',              `r34')
+define(`vme_m0',                `tmp_reg2')
+define(`tmp_reg3',              `r35')                                
+define(`vme_m1',                `tmp_reg3')
+define(`intra_flag',            `vme_m1.28')
+define(`intra_part_mask_ub',    `vme_m1.28')        
+define(`mb_intra_struct_ub',    `vme_m1.29')
+define(`tmp_reg4',              `r36')
+define(`obw_m0',                `tmp_reg4')
+define(`tmp_reg5',              `r37')
+define(`obw_m1',                `tmp_reg5')
+define(`tmp_reg6',              `r38')
+define(`obw_m2',                `tmp_reg6')
+define(`tmp_reg7',              `r39')
+define(`obw_m3',                `tmp_reg7')
+define(`tmp_reg8',              `r40')
+define(`obw_m4',                `tmp_reg8')
+define(`tmp_reg9',              `r41')
+define(`tmp_x_w',               `tmp_reg9.0')
+define(`tmp_rega',              `r42')
+define(`tmp_ud0',               `tmp_rega.0')
+define(`tmp_ud1',               `tmp_rega.4')
+define(`tmp_ud2',               `tmp_rega.8')
+define(`tmp_ud3',               `tmp_rega.12')
+define(`tmp_uw0',               `tmp_rega.0')
+define(`tmp_uw1',               `tmp_rega.2')
+define(`tmp_uw2',               `tmp_rega.4')
+define(`tmp_uw3',               `tmp_rega.6')
+define(`tmp_uw4',               `tmp_rega.8')
+define(`tmp_uw5',               `tmp_rega.10')
+define(`tmp_uw6',               `tmp_rega.12')
+define(`tmp_uw7',               `tmp_rega.14')
+
+define(`vme_m2',                `r43')
+/*
+ * MRF registers
+ */        
+
+define(`msg_ind',               `64')
+define(`msg_reg0',              `r64')
+define(`msg_reg1',              `r65')
+define(`msg_reg2',              `r66')
+define(`msg_reg3',              `r67')
+define(`msg_reg4',              `r68')
+define(`msg_reg5',              `r69')
+define(`msg_reg6',              `r70')
+define(`msg_reg7',              `r71')
+define(`msg_reg8',              `r72')
+define(`msg_reg9',              `r73')
+
+define(`ts_msg_ind',               `112')
+define(`ts_msg_reg0',               `r112')
+/*
+ * VME message payload
+ */
+
+define(`vme_msg_length',        `5')
+define(`vme_inter_wb_length',   `6')
+define(`vme_intra_wb_length',   `1')
+
+define(`vme_msg_ind',           `msg_ind')
+define(`vme_msg_0',             `msg_reg0')
+define(`vme_msg_1',             `msg_reg1')
+define(`vme_msg_2',             `msg_reg2')
+
+define(`vme_msg_3',             `msg_reg3')
+define(`vme_msg_4',             `msg_reg4')
+
+
+define(`vme_msg_5',             `msg_reg5')
+define(`vme_msg_6',             `msg_reg6')
+define(`vme_msg_7',             `msg_reg7')
+define(`vme_msg_8',             `msg_reg8')
+define(`vme_msg_9',             `msg_reg9')
+
+define(`RETURN_REG',              `r127.0')
+define(`RET_ARG',              `r127.4')
+
+/* Now at most two registers are used for input parameter */
+define(`INPUT_ARG0',              `r125')
+define(`INPUT_ARG1',              `r126')
+
+/* Two temporal registers are used in the function */
+define(`TEMP_VAR0',              `r123')
+define(`TEMP_VAR1',              `r124')
+
+
+define(`OBR_MESSAGE_TYPE',              `0')
+define(`OBR_CACHE_TYPE',                `10')
+define(`OBR_BIND_IDX',                  `BIND_IDX_OUTPUT')
+
+define(`OBR_CONTROL_0',                 `0')    /* 1 OWord, low 128 bits */
+define(`OBR_CONTROL_1',                 `1')    /* 1 OWord, high 128 bits */
+define(`OBR_CONTROL_2',                 `2')    /* 2 OWords */
+define(`OBR_CONTROL_4',                 `3')    /* 4 OWords */
+define(`OBR_CONTROL_8',                 `4')    /* 8 OWords */
+define(`OBR_WRITE_COMMIT_CATEGORY',     `0')    /* category on SNB+ for Data port */
+define(`OBR_HEADER_PRESENT',            `1')
+
+define(`mb_hwdep',           `r5.6')
+define(`MB_AVAIL',              `1:d')
+define(`MB_PRED_FLAG',          `1:w')
+
+define(`mb_pred_mode',		`r85')
+define(`mb_mvp_ref',		`r86')
+define(`mba_result',		`r87')
+define(`mbb_result',		`r88')
+define(`mbc_result',		`r89')
+define(`mb_ind',                `90')
+define(`mb_msg0',		`r90')
+define(`mb_msg_tmp',		`r91')
+define(`mb_wb',			`r92')
+define(`mb_mode_wb',		`r92')
+define(`mb_mv0',		`r93')
+define(`mb_mv1',		`r94')
+define(`mb_mv2',		`r95')
+define(`mb_mv3',		`r96')
+define(`mb_ref',		`r97')
+define(`mb_ref_win',		`r84')
+
+define(`DREF_REGION_SIZE',               `0x2020:UW')
+define(`PRED_L0',               `0x0':uw)
+define(`PRED_L1',               `0x1':uw)
+define(`PRED_BI',               `0x2':uw)
+define(`PRED_DIRECT',           `0x3':uw)
+define(`PRED_MASK',             `0x3':uw)
+
+/* The MAX search len per reference is 16 */
+define(`DSEARCH_PATH_LEN',               `0x00001212')
+define(`BI_WEIGHT',             `0x20':uw)
+define(`DSTART_CENTER',                  `0x00000000')
+define(`INTER_MASK',               	`0x03')
+define(`INTER_16X16MODE',		`0x0')
+define(`INTER_16X8MODE',		`0x01')
+define(`INTER_8X16MODE',		`0x02')
+define(`INTER_8X8MODE',			`0x03')
+define(`INTER_BLOCK0',			`0x0')
+define(`INTER_BLOCK1',			`0x1')
+define(`INTER_BLOCK2',			`0x2')
+define(`INTER_BLOCK3',			`0x3')
+define(`INTER_16X8MODE',		`0x01')
+define(`INTER_8X16MODE',		`0x02')