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| author | Xiang, Haihao <haihao.xiang@intel.com> | 2013-03-04 15:56:06 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2013-03-04 15:57:00 +0800 |
| commit | 7d34921055b21f195cea5346210f86f8292db282 (patch) | |
| tree | 6491e5a9d62d9e15d33c4e78f3c03b6e4d790394 /src | |
| parent | b3139d1a278d9daac40987f0a99c2a797c0db988 (diff) | |
| download | vaapi-intel-driver-7d34921055b21f195cea5346210f86f8292db282.tar.gz vaapi-intel-driver-7d34921055b21f195cea5346210f86f8292db282.tar.bz2 vaapi-intel-driver-7d34921055b21f195cea5346210f86f8292db282.zip | |
Update PCI IDs for Haswell CRW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 82d6940694c7a650642ccb6d68bf01b70dba4dcc)
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel_driver.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index 7e24b84..777c77f 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -201,15 +201,15 @@ struct intel_region #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A -#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */ -#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22 -#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 -#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ -#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 -#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ -#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ +#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 +#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22 +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \ devid == PCI_CHIP_Q45_G || \ |