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authorZhao Yakui <yakui.zhao@intel.com>2013-04-03 09:48:12 +0800
committerYakui Zhao <yakui.zhao@intel.com>2013-04-03 09:48:12 +0800
commitfc30b1022ba325708c9977d1e9d0e4281cd6dff2 (patch)
tree5e00d0eb2899524210d082c7ff94ccff02eef36a
parent593b6fc1fb32797ac5b7d75cb19eb70d42921e85 (diff)
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Fix the incorrect VPP parameter setting on Ivy/Haswell
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
-rwxr-xr-xsrc/i965_post_processing.h11
-rw-r--r--src/shaders/post_processing/gen7/RGB_to_YUV.g4a2
-rw-r--r--src/shaders/post_processing/gen7/rgbx_to_nv12.g75b2
-rw-r--r--src/shaders/post_processing/gen7/rgbx_to_nv12.g7b2
4 files changed, 9 insertions, 8 deletions
diff --git a/src/i965_post_processing.h b/src/i965_post_processing.h
index 4030082..66fcdef 100755
--- a/src/i965_post_processing.h
+++ b/src/i965_post_processing.h
@@ -348,16 +348,17 @@ struct gen7_pp_static_parameter
struct {
/* r2.0 */
- unsigned int pad3;
+ /* Indicates whether the rgb is swapped for the src surface
+ * 0: RGBX(MSB. X-B-G-R). 1: BGRX(MSB: X-R-G-B)
+ */
+ unsigned int src_avs_rgb_swap:1;
+ unsigned int pad3:31;
/* r2.1 */
unsigned int pad2:16;
unsigned int save_avs_rgb_swap:1; /* 0: RGB, 1: BGR */
unsigned int avs_wa_enable:1; /* must enabled for GEN7 */
- unsigned int src_avs_rgb_swap:1;
- /* Indicates whether the rgb is swapped for the src surface
- * 0: RGBX(MSB. X-B-G-R). 1: BGRX(MSB: X-R-G-B)
- */
+ unsigned int ief_enable:1;
unsigned int avs_wa_width:13;
/* 2.2 */
diff --git a/src/shaders/post_processing/gen7/RGB_to_YUV.g4a b/src/shaders/post_processing/gen7/RGB_to_YUV.g4a
index a96f857..1f0208e 100644
--- a/src/shaders/post_processing/gen7/RGB_to_YUV.g4a
+++ b/src/shaders/post_processing/gen7/RGB_to_YUV.g4a
@@ -364,7 +364,7 @@
// if channel swap?
// This means that it should be BGRX(B is the LSB) or RGBX
// 1 means that it is BGRX.
- and.nz.f0.0 null<1>:w r2.3<0;1,0>:uw 0x04:w
+ and.nz.f0.0 null<1>:w r2.0<0;1,0>:uw 0x01:w
// pointer swap
(f0.0) mov (1) uwTemp0<1> a0.0:uw
(f0.0) mov (1) a0.0:uw a0.1:uw
diff --git a/src/shaders/post_processing/gen7/rgbx_to_nv12.g75b b/src/shaders/post_processing/gen7/rgbx_to_nv12.g75b
index 96f4755..1cb9c44 100644
--- a/src/shaders/post_processing/gen7/rgbx_to_nv12.g75b
+++ b/src/shaders/post_processing/gen7/rgbx_to_nv12.g75b
@@ -501,7 +501,7 @@
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00400001, 0x22000128, 0x006902c0, 0x00000000 },
{ 0x00400001, 0x22080128, 0x006902c0, 0x00000000 },
- { 0x02800005, 0x20003d2c, 0x00000046, 0x00040004 },
+ { 0x02800005, 0x20003d2c, 0x00000040, 0x00010001 },
{ 0x00010001, 0x22200109, 0x00000200, 0x00000000 },
{ 0x00010001, 0x22000108, 0x00000202, 0x00000000 },
{ 0x00010001, 0x22020128, 0x00000220, 0x00000000 },
diff --git a/src/shaders/post_processing/gen7/rgbx_to_nv12.g7b b/src/shaders/post_processing/gen7/rgbx_to_nv12.g7b
index 098f3d8..5e11a68 100644
--- a/src/shaders/post_processing/gen7/rgbx_to_nv12.g7b
+++ b/src/shaders/post_processing/gen7/rgbx_to_nv12.g7b
@@ -501,7 +501,7 @@
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00400001, 0x22000128, 0x006902c0, 0x00000000 },
{ 0x00400001, 0x22080128, 0x006902c0, 0x00000000 },
- { 0x02800005, 0x20003d2c, 0x00000046, 0x00040004 },
+ { 0x02800005, 0x20003d2c, 0x00000040, 0x00010001 },
{ 0x00010001, 0x22200109, 0x00000200, 0x00000000 },
{ 0x00010001, 0x22000108, 0x00000202, 0x00000000 },
{ 0x00010001, 0x22020128, 0x00000220, 0x00000000 },