Add the Intra VME for I-frame on Haswell

At the same time the command buffer of MFC pak is constructed
by using CPU instead of GPU.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

10 files changed, 660 insertions, 76 deletions

diff --git a/src/gen6_vme.h b/src/gen6_vme.h
index 9231523..3b66b25 100644
--- a/src/gen6_vme.h
+++ b/src/gen6_vme.h
@@ -81,6 +81,7 @@ struct gen6_vme_context
                                             struct object_surface *obj_surface,
                                             unsigned long binding_table_offset,
                                             unsigned long surface_state_offset);
+    void *vme_state_message;
 };
 
 Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c
index b226a1b..0bd4412 100644
--- a/src/gen75_mfc.c
+++ b/src/gen75_mfc.c
@@ -42,6 +42,8 @@
 #include "gen6_mfc.h"
 #include "gen6_vme.h"
 
+#define MFC_SOFTWARE_HASWELL	1
+
 static const uint32_t gen75_mfc_batchbuffer_avc_intra[][4] = {
 #include "shaders/utils/mfc_batchbuffer_avc_intra.g7b"
 };
@@ -956,7 +958,7 @@ static void gen75_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
     }
 }
 
-#if __SOFTWARE__
+#ifdef MFC_SOFTWARE_HASWELL
 
 static int
 gen75_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb,
@@ -966,12 +968,17 @@ gen75_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb,
                               struct intel_batchbuffer *batch)
 {
     int len_in_dwords = 11;
-
+    unsigned int intra_msg;
+#define		INTRA_MSG_FLAG		(1 << 13)
+#define		INTRA_MBTYPE_MASK	(0x1F0000)
     if (batch == NULL)
         batch = encoder_context->base.batch;
 
     BEGIN_BCS_BATCH(batch, len_in_dwords);
 
+    intra_msg = msg[0] & 0xC0FF;
+    intra_msg |= INTRA_MSG_FLAG;
+    intra_msg |= ((msg[0] & INTRA_MBTYPE_MASK) >> 8);
     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
     OUT_BCS_BATCH(batch, 0);
     OUT_BCS_BATCH(batch, 0);
@@ -981,7 +988,7 @@ gen75_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb,
                   (1 << 19) |		/* CbpDcY */
                   (1 << 18) |		/* CbpDcU */
                   (1 << 17) |		/* CbpDcV */
-                  (msg[0] & 0xFFFF) );
+                  intra_msg);
 
     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);		/* Code Block Pattern for Y*/
     OUT_BCS_BATCH(batch, 0x000F000F);							/* Code Block Pattern */		
@@ -1062,6 +1069,7 @@ gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; 
     unsigned int *msg = NULL, offset = 0;
+    unsigned char *msg_ptr = NULL;
     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
@@ -1104,12 +1112,12 @@ gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
                                1, 0, 1, slice_batch);
 
     dri_bo_map(vme_context->vme_output.bo , 1);
-    msg = (unsigned int *)vme_context->vme_output.bo->virtual;
+    msg_ptr = (unsigned char *)vme_context->vme_output.bo->virtual;
 
     if (is_intra) {
-        msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
+        msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block);
     } else {
-        msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
+        msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block);
         msg += 32; /* the first 32 DWs are MVs */
         offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
     }
@@ -1119,11 +1127,11 @@ gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
         int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
         x = i % width_in_mbs;
         y = i / width_in_mbs;
+        msg = (unsigned int *) (msg_ptr + i * vme_context->vme_output.size_block);
 
         if (is_intra) {
             assert(msg);
             gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
-            msg += INTRA_VME_OUTPUT_IN_DWS;
         } else {
             if (msg[0] & INTRA_MB_FLAG_MASK) {
                 gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
@@ -1131,7 +1139,6 @@ gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
                 gen75_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
             }
 
-            msg += INTER_VME_OUTPUT_IN_DWS;
             offset += INTER_VME_OUTPUT_IN_BYTES;
         }
     }
@@ -1598,7 +1605,7 @@ gen75_mfc_avc_pipeline_programing(VADriverContextP ctx,
         return; 
     }
 
-#if __SOFTWARE__
+#ifdef MFC_SOFTWARE_HASWELL
     slice_batch_bo = gen75_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
 #else
     slice_batch_bo = gen75_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
diff --git a/src/gen75_vme.c b/src/gen75_vme.c
index c076e4f..faa9271 100644
--- a/src/gen75_vme.c
+++ b/src/gen75_vme.c
@@ -59,9 +59,11 @@
 #define CURBE_ALLOCATION_SIZE   37              /* in 256-bit */
 #define CURBE_TOTAL_DATA_LENGTH (4 * 32)        /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
 #define CURBE_URB_ENTRY_LENGTH  4               /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
+
+#define VME_MSG_LENGTH		32
   
 static const uint32_t gen75_vme_intra_frame[][4] = {
-#include "shaders/vme/intra_frame.g7b"
+#include "shaders/vme/intra_frame_haswell.g75b"
 };
 
 static const uint32_t gen75_vme_inter_frame[][4] = {
@@ -69,7 +71,7 @@ static const uint32_t gen75_vme_inter_frame[][4] = {
 };
 
 static const uint32_t gen75_vme_batchbuffer[][4] = {
-#include "shaders/vme/batchbuffer.g7b"
+#include "shaders/vme/batchbuffer.g75b"
 };
 
 static struct i965_kernel gen75_vme_kernels[] = {
@@ -161,7 +163,7 @@ gen75_vme_output_buffer_setup(VADriverContextP ctx,
     vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
 
     if (is_intra)
-        vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
+        vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
     else
         vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
 
@@ -191,7 +193,7 @@ gen75_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 
     vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
-    vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */
+    vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
     vme_context->vme_batchbuffer.pitch = 16;
     vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr, 
                                                    "VME batchbuffer",
@@ -264,8 +266,8 @@ static VAStatus gen75_vme_interface_setup(VADriverContextP ctx,
         /*Setup the descritor table*/
         memset(desc, 0, sizeof(*desc));
         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
-        desc->desc2.sampler_count = 1; /* FIXME: */
-        desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
+        desc->desc2.sampler_count = 0; /* FIXME: */
+        desc->desc2.sampler_state_pointer = 0;
         desc->desc3.binding_table_entry_count = 1; /* FIXME: */
         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
         desc->desc4.constant_urb_entry_read_offset = 0;
@@ -277,12 +279,6 @@ static VAStatus gen75_vme_interface_setup(VADriverContextP ctx,
                           0,
                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
                           kernel->bo);
-        /*Sampler State(VME state pointer)*/
-        dri_bo_emit_reloc(bo,
-                          I915_GEM_DOMAIN_INSTRUCTION, 0,
-                          (1 << 2),									//
-                          i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
-                          vme_context->vme_state.bo);
         desc++;
     }
     dri_bo_unmap(bo);
@@ -295,14 +291,18 @@ static VAStatus gen75_vme_constant_setup(VADriverContextP ctx,
                                         struct intel_encoder_context *encoder_context)
 {
     struct gen6_vme_context *vme_context = encoder_context->vme_context;
-    // unsigned char *constant_buffer;
+    unsigned char *constant_buffer;
 
     dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
     assert(vme_context->gpe_context.curbe.bo->virtual);
-    // constant_buffer = vme_context->curbe.bo->virtual;
-	
-    /*TODO copy buffer into CURB*/
+    constant_buffer = vme_context->gpe_context.curbe.bo->virtual;
 
+	/* VME MV/Mb cost table is passed by using const buffer */
+	/* Now it uses the fixed search path. So it is constructed directly
+	 * in the GPU shader.
+	 */
+    memcpy(constant_buffer, (char *)vme_context->vme_state_message, 32);
+	
     dri_bo_unmap( vme_context->gpe_context.curbe.bo);
 
     return VA_STATUS_SUCCESS;
@@ -376,9 +376,9 @@ static void gen75_vme_state_setup_fixup(VADriverContextP ctx,
         slice_param->slice_type != SLICE_TYPE_SI)
         return;
     if (encoder_context->rate_control_mode == VA_RC_CQP)
-        vme_state_message[16] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
+        vme_state_message[0] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
     else
-        vme_state_message[16] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[slice_param->slice_type].QpPrimeY];
+        vme_state_message[0] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[slice_param->slice_type].QpPrimeY];
 }
 
 static VAStatus gen75_vme_vme_state_setup(VADriverContextP ctx,
@@ -390,41 +390,22 @@ static VAStatus gen75_vme_vme_state_setup(VADriverContextP ctx,
     unsigned int *vme_state_message;
     int i;
 	
-    //building VME state message
-    dri_bo_map(vme_context->vme_state.bo, 1);
-    assert(vme_context->vme_state.bo->virtual);
-    vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
-
-    vme_state_message[0] = 0x01010101;
-    vme_state_message[1] = 0x10010101;
-    vme_state_message[2] = 0x0F0F0F0F;
-    vme_state_message[3] = 0x100F0F0F;
-    vme_state_message[4] = 0x01010101;
-    vme_state_message[5] = 0x00010101;
-    vme_state_message[6] = 0x01010101;
-    vme_state_message[7] = 0x10010101;
-    vme_state_message[8] = 0x0F0F0F0F;
-    vme_state_message[9] = 0x100F0F0F;
-    vme_state_message[10] = 0x01010101;
-    vme_state_message[11] = 0x00010101;
-    vme_state_message[12] = 0x00;
-    vme_state_message[13] = 0x00;
-
-    vme_state_message[14] = 0x4a4a;
-    vme_state_message[15] = 0x0;
-    vme_state_message[16] = 0x4a4a4a4a;
-    vme_state_message[17] = 0x4a4a4a4a;
-    vme_state_message[18] = 0x22120200;
-    vme_state_message[19] = 0x62524232;
-
-    for(i = 20; i < 32; i++) {
-        vme_state_message[i] = 0;
+    //pass the MV/Mb cost into VME message on HASWell
+    assert(vme_context->vme_state_message);
+    vme_state_message = (unsigned int *)vme_context->vme_state_message;
+
+    vme_state_message[0] = 0x4a4a4a4a;
+    vme_state_message[1] = 0x4a4a4a4a;
+    vme_state_message[2] = 0x4a4a4a4a;
+    vme_state_message[3] = 0x22120200;
+    vme_state_message[4] = 0x62524232;
+
+    for (i=5; i < 8; i++) {
+	vme_state_message[i] = 0;
     }
-    //vme_state_message[16] = 0x42424242;			//cost function LUT set 0 for Intra
 
     gen75_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
 
-    dri_bo_unmap( vme_context->vme_state.bo);
     return VA_STATUS_SUCCESS;
 }
 
@@ -437,7 +418,6 @@ gen75_vme_fill_vme_batchbuffer(VADriverContextP ctx,
                               struct intel_encoder_context *encoder_context)
 {
     struct gen6_vme_context *vme_context = encoder_context->vme_context;
-    int number_mb_cmds;
     int mb_x = 0, mb_y = 0;
     int i, s;
     unsigned int *command_ptr;
@@ -454,13 +434,6 @@ gen75_vme_fill_vme_batchbuffer(VADriverContextP ctx,
             int mb_count = i + slice_mb_begin;    
             mb_x = mb_count % mb_width;
             mb_y = mb_count / mb_width;
-            if( i == 0 ) {
-                number_mb_cmds = mb_width;          // we must mark the slice edge. 
-            } else if ( (i + 128 ) <= slice_mb_number) {
-                number_mb_cmds = 128;
-            } else {
-                number_mb_cmds = slice_mb_number - i;
-            }
 
             *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
             *command_ptr++ = kernel;
@@ -471,9 +444,9 @@ gen75_vme_fill_vme_batchbuffer(VADriverContextP ctx,
    
             /*inline data */
             *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
-            *command_ptr++ = (number_mb_cmds << 16 | transform_8x8_mode_flag | ((i==0) << 1));
+            *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | ((i==0) << 1));
 
-            i += number_mb_cmds;
+            i += 1;
         } 
     }
 
@@ -500,11 +473,7 @@ static void gen75_vme_media_init(VADriverContextP ctx, struct intel_encoder_cont
 
     /* VME state */
     dri_bo_unreference(vme_context->vme_state.bo);
-    bo = dri_bo_alloc(i965->intel.bufmgr,
-                      "Buffer",
-                      1024*16, 64);
-    assert(bo);
-    vme_context->vme_state.bo = bo;
+    vme_context->vme_state.bo = NULL;
 }
 
 static void gen75_vme_pipeline_programing(VADriverContextP ctx, 
@@ -551,8 +520,8 @@ static VAStatus gen75_vme_prepare(VADriverContextP ctx,
     /*Setup all the memory object*/
     gen75_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
     gen75_vme_interface_setup(ctx, encode_state, encoder_context);
-    gen75_vme_constant_setup(ctx, encode_state, encoder_context);
     gen75_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
+    gen75_vme_constant_setup(ctx, encode_state, encoder_context);
 
     /*Programing media pipeline*/
     gen75_vme_pipeline_programing(ctx, encode_state, encoder_context);
@@ -608,6 +577,11 @@ gen75_vme_context_destroy(void *context)
     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
     vme_context->vme_batchbuffer.bo = NULL;
 
+    if (vme_context->vme_state_message) {
+	free(vme_context->vme_state_message);
+	vme_context->vme_state_message = NULL;
+    }
+
     free(vme_context);
 }
 
@@ -641,5 +615,6 @@ Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *
     encoder_context->vme_context_destroy = gen75_vme_context_destroy;
     encoder_context->vme_pipeline = gen75_vme_pipeline;
 
+	vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int));
     return True;
 }
diff --git a/src/shaders/vme/Makefile.am b/src/shaders/vme/Makefile.am
index 80a4663..b6047c6 100644
--- a/src/shaders/vme/Makefile.am
+++ b/src/shaders/vme/Makefile.am
@@ -1,4 +1,5 @@
 VME_CORE	= batchbuffer.asm intra_frame.asm inter_frame.asm
+VME75_CORE	= batchbuffer.asm intra_frame_haswell.asm
 
 INTEL_G6B	= batchbuffer.g6b intra_frame.g6b inter_frame.g6b
 INTEL_G6A	= batchbuffer.g6a intra_frame.g6a inter_frame.g6a
@@ -10,15 +11,21 @@ INTEL_G7A	= batchbuffer.g7a intra_frame.g7a inter_frame.g7a
 INTEL_GEN7_INC	= batchbuffer.inc vme.inc
 INTEL_GEN7_ASM	= $(INTEL_G7A:%.g7a=%.gen7.asm)
 
+INTEL_G75B	= batchbuffer.g75b intra_frame_haswell.g75b
+INTEL_G75A	= batchbuffer.g75a intra_frame_haswell.g75a
+INTEL_GEN75_INC	= batchbuffer.inc vme75.inc
+INTEL_GEN75_ASM	= $(INTEL_G75A:%.g75a=%.gen75.asm)
+
 TARGETS  =
 if HAVE_GEN4ASM
 TARGETS += $(INTEL_G6B)
 TARGETS += $(INTEL_G7B)
+TARGETS += $(INTEL_G75B)
 endif
 
 all-local: $(TARGETS)
 
-SUFFIXES = .g6a .g6b .g7a .g7b .gen6.asm .gen7.asm
+SUFFIXES = .g6a .g6b .g7a .g7b .gen6.asm .gen7.asm .g75a .g75b .gen75.asm
 
 if HAVE_GEN4ASM
 $(INTEL_GEN6_ASM): $(VME_CORE) $(INTEL_GEN6_INC)
@@ -36,18 +43,31 @@ $(INTEL_GEN7_ASM): $(VME_CORE) $(INTEL_GEN7_INC)
 	rm _vme0.$@
 .gen7.asm.g7b:
 	$(AM_V_GEN)$(GEN4ASM) -g 7 -o $@ $<
+
+
+$(INTEL_GEN75_ASM): $(VME75_CORE) $(INTEL_GEN75_INC)
+.g75a.gen75.asm:
+	$(AM_V_GEN)cpp -P $< > _vme0.$@ 	&& \
+	m4 _vme0.$@ > $@				&& \
+	rm _vme0.$@
+.gen75.asm.g75b:
+	$(AM_V_GEN)$(GEN4ASM) -g 7.5 -o $@ $<
 endif
 
-CLEANFILES = $(INTEL_GEN6_ASM) $(INTEL_GEN7_ASM)
+CLEANFILES = $(INTEL_GEN6_ASM) $(INTEL_GEN7_ASM) $(INTEL_GEN75_ASM)
 
 EXTRA_DIST = \
 	$(INTEL_G6A)		\
 	$(INTEL_G6B)		\
 	$(INTEL_G7A)		\
 	$(INTEL_G7B)		\
+	$(INTEL_G75A)		\
+	$(INTEL_G75B)		\
 	$(INTEL_GEN6_INC)	\
 	$(INTEL_GEN7_INC)	\
+	$(INTEL_GEN75_INC)	\
 	$(VME_CORE)		\
+	$(VME75_CORE)		\
 	$(NULL)
 
 # Extra clean files so that maintainer-clean removes *everything*
diff --git a/src/shaders/vme/batchbuffer.g75a b/src/shaders/vme/batchbuffer.g75a
new file mode 100644
index 0000000..9a4c31a
--- /dev/null
+++ b/src/shaders/vme/batchbuffer.g75a
@@ -0,0 +1,2 @@
+#include "batchbuffer.inc"
+#include "batchbuffer.asm"
diff --git a/src/shaders/vme/batchbuffer.g75b b/src/shaders/vme/batchbuffer.g75b
new file mode 100644
index 0000000..41b0203
--- /dev/null
+++ b/src/shaders/vme/batchbuffer.g75b
@@ -0,0 +1,36 @@
+   { 0x00800001, 0x21000061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x21400061, 0x00000000, 0x00000000 },
+   { 0x00000001, 0x21140231, 0x00000014, 0x00000000 },
+   { 0x00600001, 0x22000061, 0x00000000, 0x00000000 },
+   { 0x00000001, 0x22000061, 0x00000000, 0x71000006 },
+   { 0x00000001, 0x22040221, 0x000000a5, 0x00000000 },
+   { 0x00000001, 0x221a0129, 0x000000a6, 0x00000000 },
+   { 0x00000001, 0x221c0229, 0x000000a4, 0x00000000 },
+   { 0x00000001, 0x221e0169, 0x00000000, 0x02000200 },
+   { 0x00000001, 0x21280121, 0x000000a6, 0x00000000 },
+   { 0x01000005, 0x21240c21, 0x020000a0, 0x000001ff },
+   { 0x01000005, 0x20a00c21, 0x000000a0, 0xfffffe00 },
+   { 0x00010020, 0x34001c00, 0x00001400, 0x000000b0 },
+   { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 },
+   { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 },
+   { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0205 },
+   { 0x00000040, 0x21202c21, 0x00000120, 0x02000200 },
+   { 0x0b000038, 0x21400421, 0x00000120, 0x00000128 },
+   { 0x00000009, 0x21402c21, 0x00000140, 0x00080008 },
+   { 0x00000040, 0x21400421, 0x00000140, 0x00000160 },
+   { 0x00000001, 0x22180129, 0x00000140, 0x00000000 },
+   { 0x00000040, 0x21082c21, 0x00000108, 0x00020002 },
+   { 0x01000040, 0x20a03dad, 0x000000a0, 0xfe00fe00 },
+   { 0x00110020, 0x34001c00, 0x00001400, 0xffffff50 },
+   { 0x00010020, 0x34001c00, 0x02001400, 0x00000050 },
+   { 0x00000001, 0x221e0129, 0x00000124, 0x00000000 },
+   { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 },
+   { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 },
+   { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0205 },
+   { 0x00000040, 0x21082c21, 0x00000108, 0x00020002 },
+   { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 },
+   { 0x00400001, 0x28200061, 0x00000000, 0x00000000 },
+   { 0x00000001, 0x28240061, 0x00000000, 0x05000000 },
+   { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0005 },
+   { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 },
+   { 0x07800031, 0x24001ca0, 0x00000800, 0x82000010 },
diff --git a/src/shaders/vme/intra_frame_haswell.asm b/src/shaders/vme/intra_frame_haswell.asm
new file mode 100644
index 0000000..741059e
--- /dev/null
+++ b/src/shaders/vme/intra_frame_haswell.asm
@@ -0,0 +1,195 @@
+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+// Modual name: IntraFrame.asm
+//
+// Make intra predition estimation for Intra frame
+//
+
+//
+//  Now, begin source code....
+//
+
+/*
+ * __START
+ */
+__INTRA_START:
+mov  (16) tmp_reg0.0<1>:UD      0x0:UD {align1};
+mov  (16) tmp_reg2.0<1>:UD      0x0:UD {align1};
+mov  (16) tmp_reg4.0<1>:UD      0x0:UD {align1} ;
+mov  (16) tmp_reg6.0<1>:UD      0x0:UD {align1} ;
+
+shl  (2) read0_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
+add  (1) read0_header.0<1>:D    read0_header.0<0,1,0>:D -8:W {align1};     /* X offset */
+add  (1) read0_header.4<1>:D    read0_header.4<0,1,0>:D -1:W {align1};     /* Y offset */ 
+mov  (1) read0_header.8<1>:UD   BLOCK_32X1 {align1};
+mov  (1) read0_header.20<1>:UB  thread_id_ub {align1};                  /* dispatch id */
+
+shl  (2) read1_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
+add  (1) read1_header.0<1>:D    read1_header.0<0,1,0>:D -4:W {align1};     /* X offset */
+mov  (1) read1_header.8<1>:UD   BLOCK_4X16 {align1};
+mov  (1) read1_header.20<1>:UB  thread_id_ub {align1};                  /* dispatch id */
+        
+shl  (2) vme_m0.8<1>:UW         orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
+mov  (1) vme_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
+
+mul  (1) obw_m0.8<1>:UD         w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
+add  (1) obw_m0.8<1>:UD         obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
+mul  (1) obw_m0.8<1>:UD         obw_m0.8<0,1,0>:UD 0x02:UD {align1};
+mov  (1) obw_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
+        
+/*
+ * Media Read Message -- fetch Luma neighbor edge pixels 
+ */
+/* ROW */
+mov  (8) msg_reg0.0<1>:UD       read0_header.0<8,8,1>:UD {align1};        
+send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
+
+/* COL */
+mov  (8) msg_reg0.0<1>:UD       read1_header.0<8,8,1>:UD {align1};                
+send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
+        
+/*
+ * Media Read Message -- fetch Chroma neighbor edge pixels 
+ */
+/* ROW */
+shl  (2) read0_header.0<1>:D    orig_xy_ub<2,2,1>:UB 3:UW {align1};    /* x * 16 , y * 8 */
+mul  (1) read0_header.0<1>:D    read0_header.0<0,1,0>:D  2:W {align1};
+add  (1) read0_header.0<1>:D    read0_header.0<0,1,0>:D -8:W {align1};     /* X offset */
+add  (1) read0_header.4<1>:D    read0_header.4<0,1,0>:D -1:W {align1};     /* Y offset */ 
+mov  (8) msg_reg0.0<1>:UD       read0_header.0<8,8,1>:UD {align1};        
+send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1};
+
+/* COL */
+shl  (2) read1_header.0<1>:D    orig_xy_ub<2,2,1>:UB 3:UW {align1};    /* x * 16, y * 8 */
+mul  (1) read1_header.0<1>:D    read1_header.0<0,1,0>:D  2:W {align1};
+add  (1) read1_header.0<1>:D    read1_header.0<0,1,0>:D -4:W {align1};     /* X offset */
+mov  (1) read1_header.8<1>:UD   BLOCK_8X4 {align1};
+mov  (8) msg_reg0.0<1>:UD       read1_header.0<8,8,1>:UD {align1};                
+send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1};
+
+/* m2, get the MV/Mb cost passed by constant buffer 
+when creating EU thread by MEDIA_OBJECT */       
+mov (8) vme_msg_2<1>:UD         r1.0<8,8,1>:UD {align1};
+
+/* m3 */
+mov (8) vme_msg_3<1>:UD		0x0:UD {align1};	        
+
+/* m4 */
+mov  (1) INEP_ROW.0<1>:UD       0x0:UD {align1};
+and  (1) INEP_ROW.4<1>:UD       INEP_ROW.4<0,1,0>:UD            0xFF000000:UD {align1};
+mov  (8) vme_msg_4<1>:UD         INEP_ROW.0<8,8,1>:UD {align1};
+
+/* m5 */        
+mov  (8) vme_msg_5<1>:UD         0x0:UD {align1};
+mov (16) vme_msg_5.0<1>:UB       INEP_COL0.3<32,8,4>:UB {align1};
+mov  (1) vme_msg_5.16<1>:UD      INTRA_PREDICTORE_MODE {align1};
+
+/* the penalty for Intra mode */
+mov  (1) vme_msg_5.28<1>:UD	0x010101:UD {align1};
+mov  (1) vme_msg_5.20<1>:UW      CHROMA_ROW.6<0,1,0>:UW {align1};
+
+
+/* m6 */
+
+mov  (4) vme_msg_6.16<1>:UD      CHROMA_ROW.8<4,4,1>:UD {align1};
+mov  (8) vme_msg_6.0<1>:UW       CHROMA_COL.2<16,8,2>:UW {align1};
+
+/*
+ * VME message
+ */
+/* m0 */        
+mov  (8) vme_msg_0.0<1>:UD      vme_m0.0<8,8,1>:UD {align1};
+mov  (1) tmp_reg0.0<1>:UW	LUMA_INTRA_MODE:UW {align1};
+/* Use the Luma mode */
+mov  (1) vme_msg_4.5<1>:UB	tmp_reg0.0<0,1,0>:UB {align1};
+
+/* m1 */
+mov  (1) intra_flag<1>:UW       0x0:UW {align1}                     ;
+and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1};
+(f0.0) mov  (1) intra_part_mask_ub<1>:UB  LUMA_INTRA_8x8_DISABLE {align1};
+
+cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1};                                                   /* X != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1};         /* A */
+
+cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1};                                                   /* Y != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1};          /* B */
+
+mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1};                                    /* X * Y != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1};          /* D */
+
+add  (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1};                                                        /* X + 1 */
+add  (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1};                                          /* width - (X + 1) */
+mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1};                                       /* (width - (X + 1)) * Y != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1};          /* C */
+
+and.nz.f0.0 (1) null<1>:UW slice_edge_ub<0,1,0>:UB 2:UW {align1};
+(f0.0) and (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB  0xE0 {align1};                            /* slice edge disable B,C,D*/
+
+/* Disable DC HAAR component when calculating HARR SATD block */
+mov  (1) tmp_reg0.0<1>:UW	DC_HARR_DISABLE:UW		{align1};
+mov  (1) vme_m1.30<1>:UB	tmp_reg0.0<0,1,0>:UB  {align1};
+
+/* m0 */        
+mov  (8) vme_msg_0.0<1>:UD      vme_m0.0<8,8,1>:UD {align1};
+mov  (8) vme_msg_1<1>:UD        vme_m1.0<8,8,1>:UD {align1};
+
+/* after verification it will be passed by using payload */
+send (8)
+        vme_msg_ind
+        vme_wb<1>:UD
+        null
+        cre(
+                BIND_IDX_VME,
+                VME_SIC_MESSAGE_TYPE
+        )
+        mlen sic_vme_msg_length
+        rlen vme_wb_length
+        {align1};
+/*
+ * Oword Block Write message
+ */
+mov  (8) msg_reg0.0<1>:UD       obw_m0<8,8,1>:UD {align1};
+        
+mov  (1) msg_reg1.0<1>:UD       vme_wb.0<0,1,0>:UD      {align1};
+mov  (1) msg_reg1.4<1>:UD       vme_wb.16<0,1,0>:UD     {align1};
+mov  (1) msg_reg1.8<1>:UD       vme_wb.20<0,1,0>:UD     {align1};
+mov  (1) msg_reg1.12<1>:UD      vme_wb.24<0,1,0>:UD     {align1};
+
+/* Distortion, Intra (17-16), */
+mov  (1) msg_reg1.16<1>:UW      vme_wb.12<0,1,0>:UW     {align1};
+
+mov  (1) msg_reg1.20<1>:UD      vme_wb.8<0,1,0>:UD     {align1};
+/* VME clock counts */
+mov  (1) msg_reg1.24<1>:UD      vme_wb.28<0,1,0>:UD     {align1};
+
+mov  (1) msg_reg1.28<1>:UD      obw_m0.8<0,1,0>:UD     {align1};
+
+/* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */
+send (16)
+        msg_ind
+        obw_wb
+        null
+        data_port(
+                OBW_CACHE_TYPE,
+                OBW_MESSAGE_TYPE,
+                OBW_CONTROL_2,
+                OBW_BIND_IDX,
+                OBW_WRITE_COMMIT_CATEGORY,
+                OBW_HEADER_PRESENT
+        )
+        mlen 2
+        rlen obw_wb_length
+        {align1};
+
+__EXIT: 
+/*
+ * kill thread
+ */        
+mov  (8) ts_msg_reg0<1>:UD         r0<8,8,1>:UD {align1};
+send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
diff --git a/src/shaders/vme/intra_frame_haswell.g75a b/src/shaders/vme/intra_frame_haswell.g75a
new file mode 100644
index 0000000..a690fdd
--- /dev/null
+++ b/src/shaders/vme/intra_frame_haswell.g75a
@@ -0,0 +1,2 @@
+#include "vme75.inc"
+#include "intra_frame_haswell.asm"
diff --git a/src/shaders/vme/intra_frame_haswell.g75b b/src/shaders/vme/intra_frame_haswell.g75b
new file mode 100644
index 0000000..15ad427
--- /dev/null
+++ b/src/shaders/vme/intra_frame_haswell.g75b
@@ -0,0 +1,82 @@
+   { 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24800061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 },
+   { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 },
+   { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 },
+   { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff },
+   { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f },
+   { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
+   { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 },
+   { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc },
+   { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 },
+   { 0x00000001, 0x24340231, 0x00000014, 0x00000000 },
+   { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 },
+   { 0x00000001, 0x24540231, 0x00000014, 0x00000000 },
+   { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 },
+   { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 },
+   { 0x00000041, 0x24880c21, 0x00000488, 0x00000002 },
+   { 0x00000001, 0x24940231, 0x00000014, 0x00000000 },
+   { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
+   { 0x04600031, 0x23801cb1, 0x00000800, 0x02190004 },
+   { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 },
+   { 0x04600031, 0x23a01cb1, 0x00000800, 0x02290004 },
+   { 0x00200009, 0x24002e25, 0x004500a0, 0x00030003 },
+   { 0x00000041, 0x24003ca5, 0x00000400, 0x00020002 },
+   { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 },
+   { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff },
+   { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
+   { 0x04600031, 0x26001cb1, 0x00000800, 0x02190006 },
+   { 0x00200009, 0x24202e25, 0x004500a0, 0x00030003 },
+   { 0x00000041, 0x24203ca5, 0x00000420, 0x00020002 },
+   { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc },
+   { 0x00000001, 0x242800e1, 0x00000000, 0x00070003 },
+   { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 },
+   { 0x04600031, 0x26201cb1, 0x00000800, 0x02190006 },
+   { 0x00600001, 0x28400021, 0x008d0020, 0x00000000 },
+   { 0x00600001, 0x28600061, 0x00000000, 0x00000000 },
+   { 0x00000001, 0x23800061, 0x00000000, 0x00000000 },
+   { 0x00000005, 0x23840c21, 0x00000384, 0xff000000 },
+   { 0x00600001, 0x28800021, 0x008d0380, 0x00000000 },
+   { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x28a00231, 0x00cf03a3, 0x00000000 },
+   { 0x00000001, 0x28b00061, 0x00000000, 0x11111111 },
+   { 0x00000001, 0x28bc0061, 0x00000000, 0x00010101 },
+   { 0x00000001, 0x28b40129, 0x00000606, 0x00000000 },
+   { 0x00400001, 0x28d00021, 0x00690608, 0x00000000 },
+   { 0x00600001, 0x28c00129, 0x00ae0622, 0x00000000 },
+   { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 },
+   { 0x00000001, 0x24000169, 0x00000000, 0x00010001 },
+   { 0x00000001, 0x28850231, 0x00000400, 0x00000000 },
+   { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 },
+   { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 },
+   { 0x00010001, 0x247c00f1, 0x00000000, 0x00000002 },
+   { 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 },
+   { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000060 },
+   { 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 },
+   { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000010 },
+   { 0x02000041, 0x20004628, 0x000000a0, 0x000000a1 },
+   { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000004 },
+   { 0x00000040, 0x25202e2d, 0x000000a0, 0x00010001 },
+   { 0x00000040, 0x2520352d, 0x000000a2, 0x00004520 },
+   { 0x02000041, 0x200045a0, 0x00000520, 0x000000a1 },
+   { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000008 },
+   { 0x02000005, 0x20002e28, 0x000000a4, 0x00020002 },
+   { 0x00010005, 0x247d1e31, 0x0000047d, 0x000000e0 },
+   { 0x00000001, 0x24000169, 0x00000000, 0x00200020 },
+   { 0x00000001, 0x247e0231, 0x00000400, 0x00000000 },
+   { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 },
+   { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 },
+   { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e782000 },
+   { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+   { 0x00000001, 0x28200021, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x28240021, 0x00000190, 0x00000000 },
+   { 0x00000001, 0x28280021, 0x00000194, 0x00000000 },
+   { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 },
+   { 0x00000001, 0x28300129, 0x0000018c, 0x00000000 },
+   { 0x00000001, 0x28340021, 0x00000188, 0x00000000 },
+   { 0x00000001, 0x28380021, 0x0000019c, 0x00000000 },
+   { 0x00000001, 0x283c0021, 0x00000488, 0x00000000 },
+   { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 },
+   { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 },
+   { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 },
diff --git a/src/shaders/vme/vme75.inc b/src/shaders/vme/vme75.inc
new file mode 100644
index 0000000..4643f74
--- /dev/null
+++ b/src/shaders/vme/vme75.inc
@@ -0,0 +1,264 @@
+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+// Modual name: ME_header.inc
+//
+// Global symbols define
+//
+
+/*
+ * Constant
+ */
+define(`VME_MESSAGE_TYPE_INTER',        `1')
+define(`VME_MESSAGE_TYPE_INTRA',        `2')
+define(`VME_MESSAGE_TYPE_MIXED',        `3')
+        
+define(`VME_SIC_MESSAGE_TYPE',        `1')
+define(`VME_IME_MESSAGE_TYPE',        `2')
+define(`VME_FBR_MESSAGE_TYPE',        `3')
+
+define(`BLOCK_32X1',                    `0x0000001F')
+define(`BLOCK_4X16',                    `0x000F0003')
+define(`BLOCK_8X4',                     `0x00070003')
+        
+define(`LUMA_INTRA_16x16_DISABLE',      `0x1')
+define(`LUMA_INTRA_8x8_DISABLE',        `0x2')
+define(`LUMA_INTRA_4x4_DISABLE',        `0x4')
+
+define(`INTRA_PRED_AVAIL_FLAG_AE',      `0x60')
+define(`INTRA_PRED_AVAIL_FLAG_B',       `0x10')
+define(`INTRA_PRED_AVAIL_FLAG_C',       `0x8')
+define(`INTRA_PRED_AVAIL_FLAG_D',       `0x4')
+
+define(`BIND_IDX_VME',                  `0')
+define(`BIND_IDX_VME_REF0',             `1')
+define(`BIND_IDX_VME_REF1',             `2')
+define(`BIND_IDX_OUTPUT',               `3')
+define(`BIND_IDX_INEP',                 `4')
+
+define(`SUB_PEL_MODE_INTEGER',          `0x00000000')
+define(`SUB_PEL_MODE_HALF',             `0x00001000')
+define(`SUB_PEL_MODE_QUARTER',          `0x00003000')
+
+define(`INTER_SAD_NONE',                `0x00000000')
+define(`INTER_SAD_HAAR',                `0x00200000')
+
+define(`INTRA_SAD_NONE',                `0x00000000')
+define(`INTRA_SAD_HAAR',                `0x00800000')
+
+define(`INTER_PART_MASK',               `0x00000000')
+
+define(`SEARCH_CTRL_SINGLE',            `0x00000000')
+define(`SEARCH_CTRL_DUAL_START',        `0x00000100')
+define(`SEARCH_CTRL_DUAL_RECORD',       `0x00000300')
+define(`SEARCH_CTRL_DUAL_REFERENCE',    `0x00000700')
+
+define(`REF_REGION_SIZE',               `0x2830:UW')
+
+define(`BI_SUB_MB_PART_MASK',           `0x0c000000')
+define(`MAX_NUM_MV',                    `0x00000020')
+define(`FB_PRUNING_ENABLE',             `0x40000000')
+
+define(`SEARCH_PATH_LEN',               `0x00003030')
+define(`START_CENTER',                  `0x30000000')
+
+define(`ADAPTIVE_SEARCH_ENABLE',        `0x00000002') 
+define(`INTRA_PREDICTORE_MODE',         `0x11111111:UD')
+
+define(`INTER_VME_OUTPUT_IN_OWS',       `10')
+define(`INTER_VME_OUTPUT_MV_IN_OWS',    `8')
+
+define(`INTRAMBFLAG_MASK',              `0x00002000')
+define(`MVSIZE_UW_BASE',                `0x0040')
+define(`MFC_MV32_BIT_SHIFT',            `5')
+define(`CBP_DC_YUV_UW',                 `0x000E')
+
+define(`DC_HARR_ENABLE',                `0x0000')
+define(`DC_HARR_DISABLE',		`0x0020')
+
+define(`MV32_BIT_MASK',                 `0x0020')
+define(`MV32_BIT_SHIFT',                `5')
+
+define(`OBW_CACHE_TYPE',                `10')
+
+
+define(`OBW_MESSAGE_TYPE',              `8')
+
+define(`OBW_BIND_IDX',                  `BIND_IDX_OUTPUT')
+
+define(`OBW_CONTROL_0',                 `0')    /* 1 OWord, low 128 bits */
+define(`OBW_CONTROL_1',                 `1')    /* 1 OWord, high 128 bits */
+define(`OBW_CONTROL_2',                 `2')    /* 2 OWords */
+define(`OBW_CONTROL_3',                 `3')    /* 4 OWords */
+define(`OBW_CONTROL_4',                 `4')    /* 8 OWords */
+
+
+define(`OBW_WRITE_COMMIT_CATEGORY',     `0')    /* category on Ivybridge */
+
+
+define(`OBW_HEADER_PRESENT',            `1')
+
+/* GRF registers
+ * r0 header
+ * r1~r4 constant buffer (reserved)
+ * r5 inline data
+ * r6~r11 reserved        
+ * r12 write back of VME message
+ * r13 write back of Oword Block Write        
+ */
+/*
+ * GRF 0 -- header       
+ */        
+define(`thread_id_ub',          `r0.20<0,1,0>:UB')  /* thread id in payload */
+
+/*
+ * GRF 1~4 -- Constant Buffer (reserved)
+ */
+        
+/*
+ * GRF 5 -- inline data
+ */        
+define(`inline_reg0',           `r5')
+define(`w_in_mb_uw',            `inline_reg0.2')
+define(`orig_xy_ub',            `inline_reg0.0')
+define(`orig_x_ub',             `inline_reg0.0')    /* in macroblock */    
+define(`orig_y_ub',             `inline_reg0.1')
+define(`transform_8x8_ub',      `inline_reg0.4')
+define(`slice_edge_ub',         `inline_reg0.4')
+define(`num_macroblocks',       `inline_reg0.6')
+
+/*
+ * GRF 6~11 -- reserved
+ */
+
+/*
+ * GRF 12~15 -- write back for VME message 
+ */
+define(`vme_wb',                `r12')
+define(`vme_wb0',               `r12')
+define(`vme_wb1',               `r13')
+define(`vme_wb2',               `r14')
+define(`vme_wb3',               `r15')
+define(`vme_wb4',               `r16')
+define(`vme_wb5',               `r17')
+define(`vme_wb6',               `r18')
+define(`vme_ime_wb7',		`r19')
+define(`vme_ime_wb8',		`r20')
+define(`vme_ime_wb9',		`r21')
+define(`vme_ime_wb10',		`r22')
+
+
+/*
+ * GRF 24 -- write for VME output message
+ */
+define(`obw_wb',                `null<1>:W')
+define(`obw_wb_length',         `0')
+
+
+/*
+ * GRF 28~30 -- Intra Neighbor Edge Pixels
+ */
+define(`INEP_ROW',              `r28')
+define(`INEP_COL0',             `r29')
+define(`INEP_COL1',             `r30')
+        
+/*
+ * GRF 48~50 -- Chroma Neighbor Edge Pixels
+ */
+define(`CHROMA_ROW',              `r48')
+define(`CHROMA_COL',              `r49')
+
+/*
+ * temporary registers
+ */
+define(`tmp_reg0',              `r32')
+define(`read0_header',          `tmp_reg0')
+define(`tmp_reg1',              `r33')
+define(`read1_header',          `tmp_reg1')
+define(`tmp_reg2',              `r34')
+define(`vme_m0',                `tmp_reg2')
+define(`tmp_reg3',              `r35')                                
+define(`vme_m1',                `tmp_reg3')
+define(`intra_flag',            `vme_m1.28')
+define(`intra_part_mask_ub',    `vme_m1.28')        
+define(`mb_intra_struct_ub',    `vme_m1.29')
+define(`tmp_reg4',              `r36')
+define(`obw_m0',                `tmp_reg4')
+define(`tmp_reg5',              `r37')
+define(`obw_m1',                `tmp_reg5')
+define(`tmp_reg6',              `r38')
+define(`obw_m2',                `tmp_reg6')
+define(`tmp_reg7',              `r39')
+define(`obw_m3',                `tmp_reg7')
+define(`tmp_reg8',              `r40')
+define(`obw_m4',                `tmp_reg8')
+define(`tmp_reg9',              `r41')
+define(`tmp_x_w',               `tmp_reg9.0')
+define(`tmp_rega',              `r42')
+define(`tmp_ud0',               `tmp_rega.0')
+define(`tmp_ud1',               `tmp_rega.4')
+define(`tmp_ud2',               `tmp_rega.8')
+define(`tmp_ud3',               `tmp_rega.12')
+define(`tmp_uw0',               `tmp_rega.0')
+define(`tmp_uw1',               `tmp_rega.2')
+define(`tmp_uw2',               `tmp_rega.4')
+define(`tmp_uw3',               `tmp_rega.6')
+define(`tmp_uw4',               `tmp_rega.8')
+define(`tmp_uw5',               `tmp_rega.10')
+define(`tmp_uw6',               `tmp_rega.12')
+define(`tmp_uw7',               `tmp_rega.14')
+
+/*
+ * MRF registers
+ */        
+
+define(`msg_ind',               `64')
+define(`msg_reg0',              `r64')
+define(`msg_reg1',              `r65')
+define(`msg_reg2',              `r66')
+define(`msg_reg3',              `r67')
+define(`msg_reg4',              `r68')
+define(`msg_reg5',              `r69')
+define(`msg_reg6',              `r70')
+define(`msg_reg7',              `r71')
+define(`msg_reg8',              `r72')
+define(`msg_reg9',              `r73')
+
+define(`ts_msg_ind',               `112')
+define(`ts_msg_reg0',               `r112')
+/*
+ * VME message payload
+ */
+
+define(`vme_intra_wb_length',   `1')
+define(`vme_wb_length',		`7')
+define(`sic_vme_msg_length',	`7')
+define(`fbr_vme_msg_length',	`7')
+define(`ime_vme_msg_length',	`10')
+
+define(`vme_msg_ind',           `msg_ind')
+define(`vme_msg_0',             `msg_reg0')
+define(`vme_msg_1',             `msg_reg1')
+define(`vme_msg_2',             `msg_reg2')
+
+define(`vme_msg_3',             `msg_reg3')
+define(`vme_msg_4',             `msg_reg4')
+
+
+define(`vme_msg_5',             `msg_reg5')
+define(`vme_msg_6',             `msg_reg6')
+define(`vme_msg_7',             `msg_reg7')
+define(`vme_msg_8',             `msg_reg8')
+define(`vme_msg_9',             `msg_reg9')
+
+define(`BIND_IDX_CBCR',			`6')
+
+
+define(`LUMA_CHROMA_MODE',      `0x0')
+define(`LUMA_INTRA_MODE',	`0x1')
+define(`LUMA_INTRA_DISABLE',	`0x2')