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authorXiang, Haihao <haihao.xiang@intel.com>2012-06-11 09:52:47 +0800
committerXiang, Haihao <haihao.xiang@intel.com>2012-06-11 09:52:47 +0800
commite17ce1365635a0708866199c6ad2f5ffa11407d3 (patch)
tree4299fdb80582dd37bd72a47068eb183a079caf35
parent8ac4027a75e060e2ab69b0e9b4aefaedb6f3f9d7 (diff)
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Fix slice delta for CBR mode
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
-rw-r--r--src/gen6_mfc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c
index 95a85f3..ee1272b 100644
--- a/src/gen6_mfc.c
+++ b/src/gen6_mfc.c
@@ -1344,7 +1344,7 @@ gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
if (rate_control_mode == VA_RC_CBR) {
qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
- pSliceParameter->slice_qp_delta = qp - 26;
+ pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
}
/* only support for 8-bit pixel bit-depth */
@@ -1720,7 +1720,7 @@ gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
if (rate_control_mode == VA_RC_CBR) {
qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
- pSliceParameter->slice_qp_delta = qp - 26;
+ pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
}
/* only support for 8-bit pixel bit-depth */