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| author | Dongil Park <dongil01.park@samsung.com> | 2016-06-16 14:41:06 +0900 |
|---|---|---|
| committer | jino.cho <jino.cho@samsung.com> | 2016-12-05 17:04:05 +0900 |
| commit | 6b94a57cc45a8a4578bc4bc3afd2b06c3e1f51da (patch) | |
| tree | 7368800b3b561ba5057521b92b52a90e76fb512a | |
| parent | ddeefa08d1579830559e5b2502e33d03b75b7864 (diff) | |
| download | u-boot-artik-6b94a57cc45a8a4578bc4bc3afd2b06c3e1f51da.tar.gz u-boot-artik-6b94a57cc45a8a4578bc4bc3afd2b06c3e1f51da.tar.bz2 u-boot-artik-6b94a57cc45a8a4578bc4bc3afd2b06c3e1f51da.zip | |
espresso3250: pmic: add pmic_enable_wtsr function
This patch adds pmic_enable_wtsr() to support h/w reset.
Change-Id: If810133b471cd98f862586fc006297ef74cee5a9
Signed-off-by: Dongil Park <dongil01.park@samsung.com>
| -rw-r--r-- | board/samsung/espresso3250/pmic.c | 12 | ||||
| -rw-r--r-- | board/samsung/espresso3250/pmic.h | 12 |
2 files changed, 24 insertions, 0 deletions
diff --git a/board/samsung/espresso3250/pmic.c b/board/samsung/espresso3250/pmic.c index 75a5bd98c..38a2026e3 100644 --- a/board/samsung/espresso3250/pmic.c +++ b/board/samsung/espresso3250/pmic.c @@ -269,6 +269,18 @@ void pmic_init(void) IIC0_EWrite(S2MPS14_WR_ADDR, RTC_BUF, 0x17); IIC0_EWrite(S2MPS14_WR_ADDR, BUCK2_OUT, WR_BUCK_VOLT(CONFIG_ARM_VOLT) + VDD_BASE_OFFSET); + +} + +void pmic_enable_wtsr() +{ + unsigned char buf = 0; + IIC0_ESetport(); + + IIC0_ERead(S2MPS14_RTC_RD_ADDR, RTC_WTSR_SMPL, &buf); + buf |= WTSREN; + buf |= WTSRT; + IIC0_EWrite(S2MPS14_RTC_WR_ADDR, RTC_WTSR_SMPL, buf); } void pmic_enable_peric_dev(void) diff --git a/board/samsung/espresso3250/pmic.h b/board/samsung/espresso3250/pmic.h index 1bf06fa70..f17eabc6d 100644 --- a/board/samsung/espresso3250/pmic.h +++ b/board/samsung/espresso3250/pmic.h @@ -39,6 +39,10 @@ #define S2MPS14_WR_ADDR 0xCC #define S2MPS14_RD_ADDR 0xCD +/* RTC */ +#define S2MPS14_RTC_WR_ADDR 0x0C +#define S2MPS14_RTC_RD_ADDR 0x0D + #define VDD_BASE_VOLT_BUCK1 65000 #define VDD_VOLT_STEP_BUCK1 625 #define MIN_VOLT_BUCK1 650 @@ -86,7 +90,15 @@ */ #define WRSTBI_EN (0x1 << 5) +/* + * RTC WTSR/SMPL + */ +#define RTC_WTSR_SMPL (0x1) +#define WTSREN (0x1 << 6) +#define WTSRT (0x3) + extern void pmic_init(void); +extern void pmic_enable_wtsr(void); extern void IIC0_ERead(unsigned char ChipId, unsigned char IicAddr, unsigned char *IicData); extern void IIC0_EWrite(unsigned char ChipId, |