DRM: nexell: Support LVDS voltage_level property with DTS for DRM driver

This patch support control lvds output's tx driver differential volatge level.

Change-Id: I7527705aee9fc5f22d3e6d20f50e3592a3bf16aa
Signed-off-by: jhkim <jhkim@nexell.co.kr>

3 files changed, 15 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/drm/nexell/lvds_panel.txt b/Documentation/devicetree/bindings/drm/nexell/lvds_panel.txt
index ad686d835580..efeea74f4f3e 100644
--- a/Documentation/devicetree/bindings/drm/nexell/lvds_panel.txt
+++ b/Documentation/devicetree/bindings/drm/nexell/lvds_panel.txt
@@ -14,6 +14,7 @@ Required properties for display soc panel driver:
     timing binding details.
 
  - format: lvds format 0: VESA format, 1: JEDIA foramt, 2: user location
+ - voltage_level: lvds tx driver output differential volatge level control pin
 
   - dp_control: sub node to config display port hw parameters.
    - clk_src_lv0: select display clock source of clock generator '0'
diff --git a/drivers/gpu/drm/nexell/soc/s5pxx18_dp_dev.h b/drivers/gpu/drm/nexell/soc/s5pxx18_dp_dev.h
index 0316149ddba4..8b40ede3e4e1 100644
--- a/drivers/gpu/drm/nexell/soc/s5pxx18_dp_dev.h
+++ b/drivers/gpu/drm/nexell/soc/s5pxx18_dp_dev.h
@@ -184,6 +184,7 @@ struct dp_lvds_dev {
 	int pol_inv_vs;		/* bsync polarity invert for VESA, JEIDA */
 	int pol_inv_de;		/* de polarity invert for VESA, JEIDA */
 	int pol_inv_ck;		/* input clock(pixel clock) polarity invert */
+	int voltage_level;
 	void *reset_control;
 	int num_resets;
 };
diff --git a/drivers/gpu/drm/nexell/soc/s5pxx18_dp_lvds.c b/drivers/gpu/drm/nexell/soc/s5pxx18_dp_lvds.c
index 0e127173f4b6..e8c36e37c106 100644
--- a/drivers/gpu/drm/nexell/soc/s5pxx18_dp_lvds.c
+++ b/drivers/gpu/drm/nexell/soc/s5pxx18_dp_lvds.c
@@ -24,6 +24,8 @@
 
 #include "s5pxx18_dp_dev.h"
 
+#define	DEF_VOLTAGE_LEVEL	(0x20)
+
 static void lvds_phy_reset(struct reset_control *rsc[], int num)
 {
 	int count = num;
@@ -58,6 +60,7 @@ static int nx_soc_dp_lvds_set_prepare(struct dp_control_dev *dpc,
 	struct dp_lvds_dev *dev = dpc->dp_output;
 	struct dp_ctrl_info *ctrl = &dpc->ctrl;
 	struct reset_control **rsc = dev->reset_control;
+	u32 voltage = DEF_VOLTAGE_LEVEL;
 
 	/*
 	 *-------- predefined type.
@@ -80,8 +83,10 @@ static int nx_soc_dp_lvds_set_prepare(struct dp_control_dev *dpc,
 	u32 LOC_D[7] = {ZERO,ZERO,ZERO,ZERO,ZERO,ZERO,ZERO};
 	u32 LOC_E[7] = {ZERO,ZERO,ZERO,ZERO,ZERO,ZERO,ZERO};
 
-	if (dev)
+	if (dev) {
 		format = dev->lvds_format;
+		voltage = dev->voltage_level;
+	}
 
 	pr_debug("%s: format: %d\n", __func__, format);
 
@@ -143,7 +148,7 @@ static int nx_soc_dp_lvds_set_prepare(struct dp_control_dev *dpc,
 			|	(0<<24) /* CNNCT_CNT, connectivity ctrl pin, 0:tx operating, 1: con check */
 			|	(0<<23) /* VOD_HIGH_S, VOD control pin, 1 : Vod only */
 			|	(0<<22) /* SRC_TRH, source termination resistor select pin */
-			|	(0x20/*0x3F*/<<14) /* CNT_VOD_H, TX driver output differential volatge level control pin */
+			|       (voltage<<14)
 			|	(0x01<<6) /* CNT_PEN_H, TX driver pre-emphasis level control */
 			|	(0x4<<3) /* FC_CODE, vos control pin */
 			|	(0<<2) /* OUTCON, TX Driver state selectioin pin, 0:Hi-z, 1:Low */
@@ -247,14 +252,20 @@ int nx_dp_device_lvds_register(struct device *dev,
 {
 	struct dp_lvds_dev *out;
 	u32 format;
+	u32 voltage;
 
 	out = kzalloc(sizeof(*out), GFP_KERNEL);
 	if (!out)
 		return -ENOMEM;
 
+	out->voltage_level = DEF_VOLTAGE_LEVEL;
+
 	if (!of_property_read_u32(np, "format", &format))
 		out->lvds_format = format;
 
+	if (!of_property_read_u32(np, "voltage_level", &voltage))
+		out->voltage_level = voltage;
+
 	out->reset_control = (void *)resets;
 	out->num_resets = num_resets;
 	dpc->panel_type = dp_panel_type_lvds;