From 9421bade0765d8ffb86b8a99213b611278a3542a Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 8 Jan 2013 16:36:42 +0100 Subject: pwm: atmel: add Timer Counter Block PWM driver This patch adds a PWM driver based on Atmel Timer Counter Block. The Timer Counter Block is used in Waveform generator mode. A Timer Counter Block provides up to 6 PWM devices grouped by 2: * group 0 = PWM 0 and 1 * group 1 = PWM 2 and 3 * group 2 = PMW 4 and 5 PWM devices in a given group must be configured with the same period value. If a PWM device in a group tries to change the period value and the other device is already configured with a different value an error will be returned. This driver requires device tree support. The Timer Counter Block number used to create a PWM chip is given by the tc-block field in an "atmel,tcb-pwm" compatible node. This patch was tested on kizbox board (at91sam9g20 SoC) with pwm-leds. Signed-off-by: Boris BREZILLON Signed-off-by: Thierry Reding --- drivers/pwm/Kconfig | 12 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-atmel-tcb.c | 445 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 458 insertions(+) create mode 100644 drivers/pwm/pwm-atmel-tcb.c (limited to 'drivers/pwm') diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index e513cd998170..10b6afc94bc3 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -37,6 +37,18 @@ config PWM_AB8500 To compile this driver as a module, choose M here: the module will be called pwm-ab8500. +config PWM_ATMEL_TCB + tristate "TC Block PWM" + depends on ATMEL_TCLIB && OF + help + Generic PWM framework driver for Atmel Timer Counter Block. + + A Timer Counter Block provides 6 PWM devices grouped by 2. + Devices in a given group must have the same period. + + To compile this driver as a module, choose M here: the module + will be called pwm-atmel-tcb. + config PWM_BFIN tristate "Blackfin PWM support" depends on BFIN_GPTIMERS diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 62a2963cfe58..94ba21e24bd6 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_PWM) += core.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o +obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c new file mode 100644 index 000000000000..16cb53092857 --- /dev/null +++ b/drivers/pwm/pwm-atmel-tcb.c @@ -0,0 +1,445 @@ +/* + * Copyright (C) Overkiz SAS 2012 + * + * Author: Boris BREZILLON + * License terms: GNU General Public License (GPL) version 2 + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NPWM 6 + +#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \ + ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG) + +#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \ + ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG) + +struct atmel_tcb_pwm_device { + enum pwm_polarity polarity; /* PWM polarity */ + unsigned div; /* PWM clock divider */ + unsigned duty; /* PWM duty expressed in clk cycles */ + unsigned period; /* PWM period expressed in clk cycles */ +}; + +struct atmel_tcb_pwm_chip { + struct pwm_chip chip; + spinlock_t lock; + struct atmel_tc *tc; + struct atmel_tcb_pwm_device *pwms[NPWM]; +}; + +static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct atmel_tcb_pwm_chip, chip); +} + +static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm); + + tcbpwm->polarity = polarity; + + return 0; +} + +static int atmel_tcb_pwm_request(struct pwm_chip *chip, + struct pwm_device *pwm) +{ + struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); + struct atmel_tcb_pwm_device *tcbpwm; + struct atmel_tc *tc = tcbpwmc->tc; + void __iomem *regs = tc->regs; + unsigned group = pwm->hwpwm / 2; + unsigned index = pwm->hwpwm % 2; + unsigned cmr; + int ret; + + tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL); + if (!tcbpwm) + return -ENOMEM; + + ret = clk_enable(tc->clk[group]); + if (ret) { + devm_kfree(chip->dev, tcbpwm); + return ret; + } + + pwm_set_chip_data(pwm, tcbpwm); + tcbpwm->polarity = PWM_POLARITY_NORMAL; + tcbpwm->duty = 0; + tcbpwm->period = 0; + tcbpwm->div = 0; + + spin_lock(&tcbpwmc->lock); + cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); + /* + * Get init config from Timer Counter registers if + * Timer Counter is already configured as a PWM generator. + */ + if (cmr & ATMEL_TC_WAVE) { + if (index == 0) + tcbpwm->duty = + __raw_readl(regs + ATMEL_TC_REG(group, RA)); + else + tcbpwm->duty = + __raw_readl(regs + ATMEL_TC_REG(group, RB)); + + tcbpwm->div = cmr & ATMEL_TC_TCCLKS; + tcbpwm->period = __raw_readl(regs + ATMEL_TC_REG(group, RC)); + cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK | + ATMEL_TC_BCMR_MASK); + } else + cmr = 0; + + cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0; + __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR)); + spin_unlock(&tcbpwmc->lock); + + tcbpwmc->pwms[pwm->hwpwm] = tcbpwm; + + return 0; +} + +static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); + struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm); + struct atmel_tc *tc = tcbpwmc->tc; + + clk_disable(tc->clk[pwm->hwpwm / 2]); + tcbpwmc->pwms[pwm->hwpwm] = NULL; + devm_kfree(chip->dev, tcbpwm); +} + +static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); + struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm); + struct atmel_tc *tc = tcbpwmc->tc; + void __iomem *regs = tc->regs; + unsigned group = pwm->hwpwm / 2; + unsigned index = pwm->hwpwm % 2; + unsigned cmr; + enum pwm_polarity polarity = tcbpwm->polarity; + + /* + * If duty is 0 the timer will be stopped and we have to + * configure the output correctly on software trigger: + * - set output to high if PWM_POLARITY_INVERSED + * - set output to low if PWM_POLARITY_NORMAL + * + * This is why we're reverting polarity in this case. + */ + if (tcbpwm->duty == 0) + polarity = !polarity; + + spin_lock(&tcbpwmc->lock); + cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); + + /* flush old setting and set the new one */ + if (index == 0) { + cmr &= ~ATMEL_TC_ACMR_MASK; + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_ASWTRG_CLEAR; + else + cmr |= ATMEL_TC_ASWTRG_SET; + } else { + cmr &= ~ATMEL_TC_BCMR_MASK; + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_BSWTRG_CLEAR; + else + cmr |= ATMEL_TC_BSWTRG_SET; + } + + __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR)); + + /* + * Use software trigger to apply the new setting. + * If both PWM devices in this group are disabled we stop the clock. + */ + if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) + __raw_writel(ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS, + regs + ATMEL_TC_REG(group, CCR)); + else + __raw_writel(ATMEL_TC_SWTRG, regs + + ATMEL_TC_REG(group, CCR)); + + spin_unlock(&tcbpwmc->lock); +} + +static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); + struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm); + struct atmel_tc *tc = tcbpwmc->tc; + void __iomem *regs = tc->regs; + unsigned group = pwm->hwpwm / 2; + unsigned index = pwm->hwpwm % 2; + u32 cmr; + enum pwm_polarity polarity = tcbpwm->polarity; + + /* + * If duty is 0 the timer will be stopped and we have to + * configure the output correctly on software trigger: + * - set output to high if PWM_POLARITY_INVERSED + * - set output to low if PWM_POLARITY_NORMAL + * + * This is why we're reverting polarity in this case. + */ + if (tcbpwm->duty == 0) + polarity = !polarity; + + spin_lock(&tcbpwmc->lock); + cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); + + /* flush old setting and set the new one */ + cmr &= ~ATMEL_TC_TCCLKS; + + if (index == 0) { + cmr &= ~ATMEL_TC_ACMR_MASK; + + /* Set CMR flags according to given polarity */ + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_ASWTRG_CLEAR; + else + cmr |= ATMEL_TC_ASWTRG_SET; + } else { + cmr &= ~ATMEL_TC_BCMR_MASK; + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_BSWTRG_CLEAR; + else + cmr |= ATMEL_TC_BSWTRG_SET; + } + + /* + * If duty is 0 or equal to period there's no need to register + * a specific action on RA/RB and RC compare. + * The output will be configured on software trigger and keep + * this config till next config call. + */ + if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) { + if (index == 0) { + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR; + else + cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET; + } else { + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR; + else + cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET; + } + } + + __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR)); + + if (index == 0) + __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RA)); + else + __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RB)); + + __raw_writel(tcbpwm->period, regs + ATMEL_TC_REG(group, RC)); + + /* Use software trigger to apply the new setting */ + __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, + regs + ATMEL_TC_REG(group, CCR)); + spin_unlock(&tcbpwmc->lock); + return 0; +} + +static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); + struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm); + unsigned group = pwm->hwpwm / 2; + unsigned index = pwm->hwpwm % 2; + struct atmel_tcb_pwm_device *atcbpwm = NULL; + struct atmel_tc *tc = tcbpwmc->tc; + int i; + int slowclk = 0; + unsigned period; + unsigned duty; + unsigned rate = clk_get_rate(tc->clk[group]); + unsigned long long min; + unsigned long long max; + + /* + * Find best clk divisor: + * the smallest divisor which can fulfill the period_ns requirements. + */ + for (i = 0; i < 5; ++i) { + if (atmel_tc_divisors[i] == 0) { + slowclk = i; + continue; + } + min = div_u64((u64)NSEC_PER_SEC * atmel_tc_divisors[i], rate); + max = min << tc->tcb_config->counter_width; + if (max >= period_ns) + break; + } + + /* + * If none of the divisor are small enough to represent period_ns + * take slow clock (32KHz). + */ + if (i == 5) { + i = slowclk; + rate = 32768; + min = div_u64(NSEC_PER_SEC, rate); + max = min << 16; + + /* If period is too big return ERANGE error */ + if (max < period_ns) + return -ERANGE; + } + + duty = div_u64(duty_ns, min); + period = div_u64(period_ns, min); + + if (index == 0) + atcbpwm = tcbpwmc->pwms[pwm->hwpwm + 1]; + else + atcbpwm = tcbpwmc->pwms[pwm->hwpwm - 1]; + + /* + * PWM devices provided by TCB driver are grouped by 2: + * - group 0: PWM 0 & 1 + * - group 1: PWM 2 & 3 + * - group 2: PWM 4 & 5 + * + * PWM devices in a given group must be configured with the + * same period_ns. + * + * We're checking the period value of the second PWM device + * in this group before applying the new config. + */ + if ((atcbpwm && atcbpwm->duty > 0 && + atcbpwm->duty != atcbpwm->period) && + (atcbpwm->div != i || atcbpwm->period != period)) { + dev_err(chip->dev, + "failed to configure period_ns: PWM group already configured with a different value\n"); + return -EINVAL; + } + + tcbpwm->period = period; + tcbpwm->div = i; + tcbpwm->duty = duty; + + /* If the PWM is enabled, call enable to apply the new conf */ + if (test_bit(PWMF_ENABLED, &pwm->flags)) + atmel_tcb_pwm_enable(chip, pwm); + + return 0; +} + +static const struct pwm_ops atmel_tcb_pwm_ops = { + .request = atmel_tcb_pwm_request, + .free = atmel_tcb_pwm_free, + .config = atmel_tcb_pwm_config, + .set_polarity = atmel_tcb_pwm_set_polarity, + .enable = atmel_tcb_pwm_enable, + .disable = atmel_tcb_pwm_disable, +}; + +static int atmel_tcb_pwm_probe(struct platform_device *pdev) +{ + struct atmel_tcb_pwm_chip *tcbpwm; + struct device_node *np = pdev->dev.of_node; + struct atmel_tc *tc; + int err; + int tcblock; + + err = of_property_read_u32(np, "tc-block", &tcblock); + if (err < 0) { + dev_err(&pdev->dev, + "failed to get Timer Counter Block number from device tree (error: %d)\n", + err); + return err; + } + + tc = atmel_tc_alloc(tcblock, "tcb-pwm"); + if (tc == NULL) { + dev_err(&pdev->dev, "failed to allocate Timer Counter Block\n"); + return -ENOMEM; + } + + tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL); + if (tcbpwm == NULL) { + atmel_tc_free(tc); + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + tcbpwm->chip.dev = &pdev->dev; + tcbpwm->chip.ops = &atmel_tcb_pwm_ops; + tcbpwm->chip.of_xlate = of_pwm_xlate_with_flags; + tcbpwm->chip.of_pwm_n_cells = 3; + tcbpwm->chip.base = -1; + tcbpwm->chip.npwm = NPWM; + tcbpwm->tc = tc; + + spin_lock_init(&tcbpwm->lock); + + err = pwmchip_add(&tcbpwm->chip); + if (err < 0) { + atmel_tc_free(tc); + return err; + } + + platform_set_drvdata(pdev, tcbpwm); + + return 0; +} + +static int atmel_tcb_pwm_remove(struct platform_device *pdev) +{ + struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev); + int err; + + err = pwmchip_remove(&tcbpwm->chip); + if (err < 0) + return err; + + atmel_tc_free(tcbpwm->tc); + + return 0; +} + +static const struct of_device_id atmel_tcb_pwm_dt_ids[] = { + { .compatible = "atmel,tcb-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids); + +static struct platform_driver atmel_tcb_pwm_driver = { + .driver = { + .name = "atmel-tcb-pwm", + .of_match_table = atmel_tcb_pwm_dt_ids, + }, + .probe = atmel_tcb_pwm_probe, + .remove = atmel_tcb_pwm_remove, +}; +module_platform_driver(atmel_tcb_pwm_driver); + +MODULE_AUTHOR("Boris BREZILLON "); +MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 8ab432caa46413c9f3ca81d82ea9fa5bae07c3c1 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Thu, 3 Jan 2013 08:44:15 +1300 Subject: pwm: vt8500: Register write busy test performed incorrectly Correct operation for register writes is to perform a busy-wait after writing the register. Currently the busy wait it performed before, meaning subsequent register writes to bitfields may occur before the previous field has been updated. Also, all registers are defined as 32-bit read/write. Change pwm_busy_wait() to use readl rather than readb. Improve readability of code with defines for registers and bitfields. Signed-off-by: Tony Prisk Signed-off-by: Thierry Reding --- drivers/pwm/pwm-vt8500.c | 64 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 49 insertions(+), 15 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-vt8500.c b/drivers/pwm/pwm-vt8500.c index b0ba2d403439..bbc37504103a 100644 --- a/drivers/pwm/pwm-vt8500.c +++ b/drivers/pwm/pwm-vt8500.c @@ -36,6 +36,25 @@ */ #define VT8500_NR_PWMS 2 +#define REG_CTRL(pwm) (((pwm) << 4) + 0x00) +#define REG_SCALAR(pwm) (((pwm) << 4) + 0x04) +#define REG_PERIOD(pwm) (((pwm) << 4) + 0x08) +#define REG_DUTY(pwm) (((pwm) << 4) + 0x0C) +#define REG_STATUS 0x40 + +#define CTRL_ENABLE BIT(0) +#define CTRL_INVERT BIT(1) +#define CTRL_AUTOLOAD BIT(2) +#define CTRL_STOP_IMM BIT(3) +#define CTRL_LOAD_PRESCALE BIT(4) +#define CTRL_LOAD_PERIOD BIT(5) + +#define STATUS_CTRL_UPDATE BIT(0) +#define STATUS_SCALAR_UPDATE BIT(1) +#define STATUS_PERIOD_UPDATE BIT(2) +#define STATUS_DUTY_UPDATE BIT(3) +#define STATUS_ALL_UPDATE 0x0F + struct vt8500_chip { struct pwm_chip chip; void __iomem *base; @@ -45,15 +64,17 @@ struct vt8500_chip { #define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip) #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) -static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask) +static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask) { int loops = msecs_to_loops(10); - while ((readb(reg) & bitmask) && --loops) + u32 mask = bitmask << (nr << 8); + + while ((readl(vt8500->base + REG_STATUS) & mask) && --loops) cpu_relax(); if (unlikely(!loops)) - pr_warn("Waiting for status bits 0x%x to clear timed out\n", - bitmask); + dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n", + mask); } static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -63,6 +84,7 @@ static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, unsigned long long c; unsigned long period_cycles, prescale, pv, dc; int err; + u32 val; err = clk_enable(vt8500->clk); if (err < 0) { @@ -91,14 +113,19 @@ static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, do_div(c, period_ns); dc = c; - pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 1)); - writel(prescale, vt8500->base + 0x4 + (pwm->hwpwm << 4)); + writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE); + + writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE); - pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 2)); - writel(pv, vt8500->base + 0x8 + (pwm->hwpwm << 4)); + writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE); - pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 3)); - writel(dc, vt8500->base + 0xc + (pwm->hwpwm << 4)); + val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); + val |= CTRL_AUTOLOAD; + writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); clk_disable(vt8500->clk); return 0; @@ -106,8 +133,9 @@ static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - int err; struct vt8500_chip *vt8500 = to_vt8500_chip(chip); + int err; + u32 val; err = clk_enable(vt8500->clk); if (err < 0) { @@ -115,17 +143,23 @@ static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) return err; } - pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 0)); - writel(5, vt8500->base + (pwm->hwpwm << 4)); + val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); + val |= CTRL_ENABLE; + writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); + return 0; } static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct vt8500_chip *vt8500 = to_vt8500_chip(chip); + u32 val; - pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 0)); - writel(0, vt8500->base + (pwm->hwpwm << 4)); + val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); + val &= ~CTRL_ENABLE; + writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); clk_disable(vt8500->clk); } -- cgit v1.2.3 From 3ccb1c1702ed4bb07006d20c8173899a69dae242 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Thu, 3 Jan 2013 08:44:16 +1300 Subject: pwm: vt8500: Add polarity support Add support to set polarity on PWM devices, allowing for inverted duty cycles. Also update the binding document to #pwm-cells = <3> to allow passing the flags from devicetree. Signed-off-by: Tony Prisk Signed-off-by: Thierry Reding --- drivers/pwm/pwm-vt8500.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-vt8500.c b/drivers/pwm/pwm-vt8500.c index bbc37504103a..98d79e9f0144 100644 --- a/drivers/pwm/pwm-vt8500.c +++ b/drivers/pwm/pwm-vt8500.c @@ -164,10 +164,31 @@ static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) clk_disable(vt8500->clk); } +static int vt8500_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct vt8500_chip *vt8500 = to_vt8500_chip(chip); + u32 val; + + val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); + + if (polarity == PWM_POLARITY_INVERSED) + val |= CTRL_INVERT; + else + val &= ~CTRL_INVERT; + + writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); + + return 0; +} + static struct pwm_ops vt8500_pwm_ops = { .enable = vt8500_pwm_enable, .disable = vt8500_pwm_disable, .config = vt8500_pwm_config, + .set_polarity = vt8500_pwm_set_polarity, .owner = THIS_MODULE, }; @@ -197,6 +218,8 @@ static int vt8500_pwm_probe(struct platform_device *pdev) chip->chip.dev = &pdev->dev; chip->chip.ops = &vt8500_pwm_ops; + chip->chip.of_xlate = of_pwm_xlate_with_flags; + chip->chip.of_pwm_n_cells = 3; chip->chip.base = -1; chip->chip.npwm = VT8500_NR_PWMS; -- cgit v1.2.3 From 0074b49b3fa0886047413dbca0508594b1d80c61 Mon Sep 17 00:00:00 2001 From: "Philip, Avinash" Date: Thu, 10 Jan 2013 18:35:26 +0530 Subject: pwm: pwm-tiehrpwm: Update the clock handling of pwm-tiehrpwm driver The clock framework has changed and it's now better to invoke clock_prepare_enable() and clk_disable_unprepare() rather than the legacy clk_enable() and clk_disable() calls. This patch converts the pwm-tiehrpwm driver to the new framework. Signed-off-by: Philip Avinash Signed-off-by: Thierry Reding --- drivers/pwm/pwm-tiehrpwm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 72a6dd40c9ec..4fcafbfba60e 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -318,6 +318,7 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); unsigned short aqcsfrc_val, aqcsfrc_mask; + int ret; /* Leave clock enabled on enabling PWM */ pm_runtime_get_sync(chip->dev); @@ -341,7 +342,12 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) configure_polarity(pc, pwm->hwpwm); /* Enable TBCLK before enabling PWM device */ - clk_enable(pc->tbclk); + ret = clk_prepare_enable(pc->tbclk); + if (ret) { + pr_err("Failed to enable TBCLK for %s\n", + dev_name(pc->chip.dev)); + return ret; + } /* Enable time counter for free_run */ ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN); @@ -372,7 +378,7 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); /* Disabling TBCLK on PWM disable */ - clk_disable(pc->tbclk); + clk_disable_unprepare(pc->tbclk); /* Stop Time base counter */ ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT); -- cgit v1.2.3 From 0e2feb17dec9d97f6b44d5af872633f7ffba9ffb Mon Sep 17 00:00:00 2001 From: Philip Avinash Date: Thu, 17 Jan 2013 14:50:02 +0530 Subject: pwm: pwm-tiehrpwm: Low power sleep support In low power modes of AM33XX platforms, peripherals power is cut off. This patch supports low power sleep transition support for EHRPWM driver. Signed-off-by: Philip Avinash Signed-off-by: Thierry Reding --- drivers/pwm/pwm-tiehrpwm.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 4fcafbfba60e..33e15c4fba02 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -113,6 +113,17 @@ #define NUM_PWM_CHANNEL 2 /* EHRPWM channels */ +struct ehrpwm_context { + u16 tbctl; + u16 tbprd; + u16 cmpa; + u16 cmpb; + u16 aqctla; + u16 aqctlb; + u16 aqsfrc; + u16 aqcsfrc; +}; + struct ehrpwm_pwm_chip { struct pwm_chip chip; unsigned int clk_rate; @@ -120,6 +131,7 @@ struct ehrpwm_pwm_chip { unsigned long period_cycles[NUM_PWM_CHANNEL]; enum pwm_polarity polarity[NUM_PWM_CHANNEL]; struct clk *tbclk; + struct ehrpwm_context ctx; }; static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip) @@ -127,6 +139,11 @@ static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip) return container_of(chip, struct ehrpwm_pwm_chip, chip); } +static u16 ehrpwm_read(void *base, int offset) +{ + return readw(base + offset); +} + static void ehrpwm_write(void *base, int offset, unsigned int val) { writew(val & 0xFFFF, base + offset); @@ -516,11 +533,77 @@ static int ehrpwm_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&pc->chip); } +void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc) +{ + pm_runtime_get_sync(pc->chip.dev); + pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL); + pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD); + pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA); + pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB); + pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA); + pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB); + pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC); + pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC); + pm_runtime_put_sync(pc->chip.dev); +} + +void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc) +{ + ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd); + ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa); + ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb); + ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla); + ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb); + ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc); + ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc); + ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl); +} + +static int ehrpwm_pwm_suspend(struct device *dev) +{ + struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev); + int i; + + ehrpwm_pwm_save_context(pc); + for (i = 0; i < pc->chip.npwm; i++) { + struct pwm_device *pwm = &pc->chip.pwms[i]; + + if (!test_bit(PWMF_ENABLED, &pwm->flags)) + continue; + + /* Disable explicitly if PWM is running */ + pm_runtime_put_sync(dev); + } + return 0; +} + +static int ehrpwm_pwm_resume(struct device *dev) +{ + struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev); + int i; + + for (i = 0; i < pc->chip.npwm; i++) { + struct pwm_device *pwm = &pc->chip.pwms[i]; + + if (!test_bit(PWMF_ENABLED, &pwm->flags)) + continue; + + /* Enable explicitly if PWM was running */ + pm_runtime_get_sync(dev); + } + ehrpwm_pwm_restore_context(pc); + return 0; +} + +static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend, + ehrpwm_pwm_resume); + static struct platform_driver ehrpwm_pwm_driver = { .driver = { .name = "ehrpwm", .owner = THIS_MODULE, .of_match_table = ehrpwm_of_match, + .pm = &ehrpwm_pwm_pm_ops, }, .probe = ehrpwm_pwm_probe, .remove = ehrpwm_pwm_remove, -- cgit v1.2.3 From 0d75c203effefa4f62ca4d30bf52bd9ec246717f Mon Sep 17 00:00:00 2001 From: Philip Avinash Date: Thu, 17 Jan 2013 14:50:03 +0530 Subject: pwm: pwm-tiecap: Low power sleep support In low power modes of AM33XX platforms, peripherals power is cut off. This patch supports low power sleep transition support for ECAP driver. Signed-off-by: Philip Avinash Signed-off-by: Thierry Reding --- drivers/pwm/pwm-tiecap.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c index 5cf016dd9822..05b676db88e6 100644 --- a/drivers/pwm/pwm-tiecap.c +++ b/drivers/pwm/pwm-tiecap.c @@ -41,10 +41,17 @@ #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6)) #define ECCTL2_TSCTR_FREERUN BIT(4) +struct ecap_context { + u32 cap3; + u32 cap4; + u16 ecctl2; +}; + struct ecap_pwm_chip { struct pwm_chip chip; unsigned int clk_rate; void __iomem *mmio_base; + struct ecap_context ctx; }; static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip) @@ -288,11 +295,57 @@ static int ecap_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&pc->chip); } +void ecap_pwm_save_context(struct ecap_pwm_chip *pc) +{ + pm_runtime_get_sync(pc->chip.dev); + pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2); + pc->ctx.cap4 = readl(pc->mmio_base + CAP4); + pc->ctx.cap3 = readl(pc->mmio_base + CAP3); + pm_runtime_put_sync(pc->chip.dev); +} + +void ecap_pwm_restore_context(struct ecap_pwm_chip *pc) +{ + writel(pc->ctx.cap3, pc->mmio_base + CAP3); + writel(pc->ctx.cap4, pc->mmio_base + CAP4); + writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2); +} + +static int ecap_pwm_suspend(struct device *dev) +{ + struct ecap_pwm_chip *pc = dev_get_drvdata(dev); + struct pwm_device *pwm = pc->chip.pwms; + + ecap_pwm_save_context(pc); + + /* Disable explicitly if PWM is running */ + if (test_bit(PWMF_ENABLED, &pwm->flags)) + pm_runtime_put_sync(dev); + + return 0; +} + +static int ecap_pwm_resume(struct device *dev) +{ + struct ecap_pwm_chip *pc = dev_get_drvdata(dev); + struct pwm_device *pwm = pc->chip.pwms; + + /* Enable explicitly if PWM was running */ + if (test_bit(PWMF_ENABLED, &pwm->flags)) + pm_runtime_get_sync(dev); + + ecap_pwm_restore_context(pc); + return 0; +} + +static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume); + static struct platform_driver ecap_pwm_driver = { .driver = { .name = "ecap", .owner = THIS_MODULE, .of_match_table = ecap_of_match, + .pm = &ecap_pwm_pm_ops, }, .probe = ecap_pwm_probe, .remove = ecap_pwm_remove, -- cgit v1.2.3 From 6e69ab1361c44e3ee1398158b56d114b1aef8179 Mon Sep 17 00:00:00 2001 From: Florian Vaussard Date: Mon, 28 Jan 2013 15:00:57 +0100 Subject: pwm: Add pwm_can_sleep() as exported API to users Calls to some external PWM chips can sleep. To help users, add pwm_can_sleep() API. Cc: Thierry Reding Cc: Peter Ujfalusi Signed-off-by: Florian Vaussard Reviewed-by: Peter Ujfalusi Signed-off-by: Thierry Reding --- drivers/pwm/core.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/pwm') diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 903138b18842..ffbef95e88dc 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -733,6 +733,18 @@ void devm_pwm_put(struct device *dev, struct pwm_device *pwm) } EXPORT_SYMBOL_GPL(devm_pwm_put); +/** + * pwm_can_sleep() - report whether PWM access will sleep + * @pwm: PWM device + * + * It returns true if accessing the PWM can sleep, false otherwise. + */ +bool pwm_can_sleep(struct pwm_device *pwm) +{ + return pwm->chip->can_sleep; +} +EXPORT_SYMBOL_GPL(pwm_can_sleep); + #ifdef CONFIG_DEBUG_FS static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s) { -- cgit v1.2.3 From 2e2a0f6ed1637e8cc4c33850bdf51a418d516157 Mon Sep 17 00:00:00 2001 From: Florian Vaussard Date: Mon, 28 Jan 2013 15:00:58 +0100 Subject: pwm: Add can_sleep property to drivers Calls to PWM drivers connected through I2C can sleep. Use the new can_sleep property. Acked-by: Peter Ujfalusi Signed-off-by: Florian Vaussard Signed-off-by: Thierry Reding --- drivers/pwm/pwm-twl-led.c | 1 + drivers/pwm/pwm-twl.c | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-twl-led.c b/drivers/pwm/pwm-twl-led.c index 9dfa0f3eca30..83e25d45d640 100644 --- a/drivers/pwm/pwm-twl-led.c +++ b/drivers/pwm/pwm-twl-led.c @@ -300,6 +300,7 @@ static int twl_pwmled_probe(struct platform_device *pdev) twl->chip.dev = &pdev->dev; twl->chip.base = -1; + twl->chip.can_sleep = true; mutex_init(&twl->mutex); diff --git a/drivers/pwm/pwm-twl.c b/drivers/pwm/pwm-twl.c index e65db95d5e59..f783efcd14bb 100644 --- a/drivers/pwm/pwm-twl.c +++ b/drivers/pwm/pwm-twl.c @@ -315,6 +315,7 @@ static int twl_pwm_probe(struct platform_device *pdev) twl->chip.dev = &pdev->dev; twl->chip.base = -1; twl->chip.npwm = 2; + twl->chip.can_sleep = true; mutex_init(&twl->mutex); -- cgit v1.2.3 From b133d2a1370c9b8c9d4b64eaa07e17c86f51b004 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 30 Jan 2013 09:19:55 +0100 Subject: pwm: Make Kconfig entries more consistent PWM is now consistently spelled in all uppercase letters. For the Atmel driver the entry now also mentions Atmel to make it easier to find. Signed-off-by: Thierry Reding --- drivers/pwm/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 10b6afc94bc3..0e0bfa035083 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -38,7 +38,7 @@ config PWM_AB8500 will be called pwm-ab8500. config PWM_ATMEL_TCB - tristate "TC Block PWM" + tristate "Atmel TC Block PWM support" depends on ATMEL_TCLIB && OF help Generic PWM framework driver for Atmel Timer Counter Block. @@ -59,7 +59,7 @@ config PWM_BFIN will be called pwm-bfin. config PWM_IMX - tristate "i.MX pwm support" + tristate "i.MX PWM support" depends on ARCH_MXC help Generic PWM framework driver for i.MX. @@ -116,7 +116,7 @@ config PWM_PXA will be called pwm-pxa. config PWM_SAMSUNG - tristate "Samsung pwm support" + tristate "Samsung PWM support" depends on PLAT_SAMSUNG help Generic PWM framework driver for Samsung. @@ -195,7 +195,7 @@ config PWM_TWL_LED will be called pwm-twl-led. config PWM_VT8500 - tristate "vt8500 pwm support" + tristate "vt8500 PWM support" depends on ARCH_VT8500 help Generic PWM framework driver for vt8500. -- cgit v1.2.3 From 928c44775bbf312332c5cb8df7c7451c1d8fba25 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 30 Jan 2013 09:22:24 +0100 Subject: pwm: Export pwm_{set,get}_chip_data() When building a driver as a module, these functions need to be exported for linking to succeed. Signed-off-by: Thierry Reding --- drivers/pwm/core.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/pwm') diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index ffbef95e88dc..7d6081879c13 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -211,6 +211,7 @@ int pwm_set_chip_data(struct pwm_device *pwm, void *data) return 0; } +EXPORT_SYMBOL_GPL(pwm_set_chip_data); /** * pwm_get_chip_data() - get private chip data for a PWM @@ -220,6 +221,7 @@ void *pwm_get_chip_data(struct pwm_device *pwm) { return pwm ? pwm->chip_data : NULL; } +EXPORT_SYMBOL_GPL(pwm_get_chip_data); /** * pwmchip_add() - register a new PWM chip -- cgit v1.2.3 From 838bf09d4fa01d39417e42c731aa31d7a256fb7c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 15 Feb 2013 15:02:22 -0700 Subject: pwm: tegra: assume CONFIG_OF Tegra only supports, and always enables, device tree. Remove all ifdefs for DT support from the driver. Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding --- drivers/pwm/pwm-tegra.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 30c0e2b70ce8..f7770312c1a9 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -233,7 +233,6 @@ static int tegra_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&pc->chip); } -#ifdef CONFIG_OF static struct of_device_id tegra_pwm_of_match[] = { { .compatible = "nvidia,tegra20-pwm" }, { .compatible = "nvidia,tegra30-pwm" }, @@ -241,12 +240,11 @@ static struct of_device_id tegra_pwm_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); -#endif static struct platform_driver tegra_pwm_driver = { .driver = { .name = "tegra-pwm", - .of_match_table = of_match_ptr(tegra_pwm_of_match), + .of_match_table = tegra_pwm_of_match, }, .probe = tegra_pwm_probe, .remove = tegra_pwm_remove, -- cgit v1.2.3 From 30f786170352b8264bc7b61c2482713e54accec8 Mon Sep 17 00:00:00 2001 From: Johannes Thumshirn Date: Sat, 16 Feb 2013 19:20:51 +0100 Subject: pwm: twl: Use to_twl() instead of container_of() Always use to_twl() for converting into private data instead of container_of(). Signed-off-by: Johannes Thumshirn Signed-off-by: Thierry Reding --- drivers/pwm/pwm-twl.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-twl.c b/drivers/pwm/pwm-twl.c index f783efcd14bb..bf3fda294223 100644 --- a/drivers/pwm/pwm-twl.c +++ b/drivers/pwm/pwm-twl.c @@ -200,8 +200,7 @@ out: static void twl4030_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) { - struct twl_pwm_chip *twl = container_of(chip, struct twl_pwm_chip, - chip); + struct twl_pwm_chip *twl = to_twl(chip); int ret; u8 val, mask; @@ -231,8 +230,7 @@ out: static int twl6030_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct twl_pwm_chip *twl = container_of(chip, struct twl_pwm_chip, - chip); + struct twl_pwm_chip *twl = to_twl(chip); int ret; u8 val; @@ -255,8 +253,7 @@ out: static void twl6030_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct twl_pwm_chip *twl = container_of(chip, struct twl_pwm_chip, - chip); + struct twl_pwm_chip *twl = to_twl(chip); int ret; u8 val; -- cgit v1.2.3