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2011-12-27Merge branch 'tegra/cleanup' into next/cleanupArnd Bergmann3-35/+13
* tegra/cleanup: arm/tegra: Remove code that's ifndef CONFIG_ARM_GIC arm/tegra: remove unused defines arm/tegra: fix variable formatting in makefile Conflicts: arch/arm/mach-tegra/include/mach/entry-macro.S
2011-12-21arm/at91: fix build of stamp9g20Olof Johansson1-2/+2
Fixes build: arch/arm/mach-at91/board-stamp9g20.c:126: error: expected '}' before ';' token Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2011-12-20Merge branch 'u300/cleanup' into next/cleanupOlof Johansson3-21/+1
* u300/cleanup: ARM: u300: delete memory.h
2011-12-19Merge branch 'picoxcell/cleanup' into next/cleanupOlof Johansson402-3628/+3045
* picoxcell/cleanup: (4 commits) MAINTAINERS: add maintainer entry for Picochip picoxcell ARM: picoxcell: move io mappings to common.c ARM: picoxcell: don't reserve irq_descs ARM: picoxcell: remove mach/memory.h Conflicts: arch/arm/mach-at91/setup.c
2011-12-19ARM: u300: delete memory.hLinus Walleij3-21/+1
Last merge window the memory maps for U300 were simplified so we can now safely delete memory.h. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-12-18ARM: picoxcell: move io mappings to common.cJamie Iles4-34/+13
Now that we have lost our machine specific ioremap() we just have one mapping that covers all peripherals. Move this to common.c to simplify things a little. Signed-off-by: Jamie Iles <jamie@jamieiles.com>
2011-12-18ARM: picoxcell: don't reserve irq_descsJamie Iles3-8/+4
All irq_desc's are now dynamically allocated so we don't need to statically reserve them. v2: - select SPARSE_IRQ and set .nr_irqs to NR_IRQS_LEGACY to skip ISA and IRQ 0. Signed-off-by: Jamie Iles <jamie@jamieiles.com>
2011-12-18ARM: picoxcell: remove mach/memory.hJamie Iles1-1/+0
mach/memory.h is no longer required for simple platforms so remove it for picoxcell. Signed-off-by: Jamie Iles <jamie@jamieiles.com>
2011-12-16Merge branch 'davinci/cleanup' into next/cleanupArnd Bergmann1-52/+1
2011-12-15Merge branch 'at91/defconfig' into next/cleanupOlof Johansson120-611/+775
2011-12-15ARM: at91: delete the pcontrol_g20_defconfigPaul Gortmaker1-175/+0
In routine testing I found this file should not specify a site specific toolchain path. I suggested that the defconfigs should not be calling out site specific toolchain locations, so we should delete the setting of CROSS_COMPILE. In response, it was indicated that this is an obsolete defconfig and it should simply be deleted. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
2011-12-12ARM: kexec: use soft_restart for branching to the reboot bufferWill Deacon1-12/+3
Now that there is a common way to reset the machine, let's use it instead of reinventing the wheel in the kexec backend. Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-12-12ARM: stop: execute platform callback from cpu_stop codeWill Deacon2-1/+5
Sending IPI_CPU_STOP to a CPU causes it to execute a busy cpu_relax loop forever. This makes it impossible to kexec successfully on an SMP system since the secondary CPUs do not reset. This patch adds a callback to platform_cpu_kill, defined when CONFIG_HOTPLUG_CPU=y, from the ipi_cpu_stop handling code. This function currently just returns 1 on all platforms that define it but allows them to do something more sophisticated in the future. Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-12-12ARM: reset: implement soft_restart for jumping to a physical addressWill Deacon1-10/+40
Tools such as kexec and CPU hotplug require a way to reset the processor and branch to some code in physical space. This requires various bits of jiggery pokery with the caches and MMU which, when it goes wrong, tends to lock up the system. This patch fleshes out the soft_restart implementation so that it branches to the reset code using the identity mapping. This requires us to change to a temporary stack, held within the kernel image as a static array, to avoid conflicting with the new view of memory. Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-12-12ARM: lib: add call_with_stack function for safely changing stackWill Deacon2-1/+46
When disabling the MMU, it is necessary to take out a 1:1 identity map of the reset code so that it can safely be executed with and without the MMU active. To avoid the situation where the physical address of the reset code aliases with the virtual address of the active stack (which cannot be included in the 1:1 mapping), it is desirable to change to a new stack at a location which is less likely to alias. This code adds a new lib function, call_with_stack: void call_with_stack(void (*fn)(void *), void *arg, void *sp); which changes the stack to point at the sp parameter, before invoking fn(arg) with the new stack selected. Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-12-11ARM: 7183/1: vic: register the VIC for ST-modified VIC'sJamie Iles1-2/+3
When probing the VIC, the ST variant has a different probing method to account for the extra interrupts which meant we didn't previously call vic_register() which registered the irq_domain. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-12-09Merge branch 'iommu/fixes' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu * 'iommu/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: MAINTAINERS: Update amd-iommu F: patterns iommu/amd: Fix typo in kernel-parameters.txt iommu/msm: Fix compile error in mach-msm/devices-iommu.c Fix comparison using wrong pointer variable in dma debug code
2011-12-08Merge branch 'fixes' of ↵Linus Torvalds28-55/+69
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits) ARM: sa1100: fix build error ARM: OMAP1: recalculate loops per jiffy after dpll1 reprogram ARM: davinci: dm365 evm: align nand partition table to u-boot ARM: davinci: da850 evm: change audio edma event queue to EVENTQ_0 ARM: davinci: dm646x evm: wrong register used in setup_vpif_input_channel_mode ARM: davinci: dm646x does not have a DSP domain ARM: davinci: psc: fix incorrect offsets ARM: davinci: psc: fix incorrect mask ARM: mx28: LRADC macro rename arm: mx23: recognise stmp378x as mx23 ARM: mxs: fix machines' initializers order ARM: mxs/tx28: add __initconst for fec pdata ARM: S3C64XX: Staticise s3c6400_sysclass ARM: S3C64XX: Add linux/export.h to dev-spi.c ARM: S3C64XX: Remove extern from definition of framebuffer setup call MAINTAINERS: Extend Samsung patterns to cover SPI and ASoC drivers MAINTAINERS: Add linux-samsung-soc mailing list for Samsung MAINTAINERS: Consolidate Samsung MAINTAINERS ARM: CSR: PM: fix build error due to undeclared 'THIS_MODULE' ARM: CSR: fix build error due to new mdesc->dma_zone_size ...
2011-12-08Merge branch 'for-rmk' of ↵Russell King32-322/+1199
git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux into devel-stable Conflicts: arch/arm/mm/ioremap.c
2011-12-08Merge branch 'fixes' of git://github.com/hzhuang1/linux into fixesArnd Bergmann1-2/+2
2011-12-08ARM: LPAE: Add the Kconfig entriesCatalin Marinas2-1/+18
This patch adds the ARM_LPAE and ARCH_PHYS_ADDR_T_64BIT Kconfig entries allowing LPAE support to be compiled into the kernel. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: mark memory banks with start > ULONG_MAX as highmemWill Deacon1-1/+15
Memory banks living outside of the 32-bit physical address space do not have a 1:1 pa <-> va mapping and therefore the __va macro may wrap. This patch ensures that such banks are marked as highmem so that the Kernel doesn't try to split them up when it sees that the wrapped virtual address overlaps the vmalloc space. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org>
2011-12-08ARM: LPAE: Add identity mapping support for the 3-level page table formatCatalin Marinas1-1/+27
With LPAE, the pgd is a separate page table with entries pointing to the pmd. The identity_mapping_add() function needs to ensure that the pgd is populated before populating the pmd level. The do..while blocks now loop over the pmd in order to have the same implementation for the two page table formats. The pmd_addr_end() definition has been removed and the generic one used instead. The pmd clean-up is done in the pgd_free() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: Add context switching supportCatalin Marinas1-2/+17
With LPAE, TTBRx registers are 64-bit. The ASID is stored in TTBR0 rather than a separate Context ID register. This patch makes the necessary changes to handle context switching on LPAE. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: Add fault handling supportCatalin Marinas6-5/+104
The DFSR and IFSR register format is different when LPAE is enabled. In addition, DFSR and IFSR have similar definitions for the fault type. This modifies the fault code to correctly handle the new format. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: Invalidate the TLB before freeing the PMDCatalin Marinas1-1/+10
Similar to the PTE freeing, this patch introduced __pmd_free_tlb() which invalidates the TLB before freeing a PMD page. This is needed because on newer processors the entry in the upper page table may be cached by the TLB and point to random data after the PMD has been freed. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: MMU setup for the 3-level page table formatCatalin Marinas5-12/+243
This patch adds the MMU initialisation for the LPAE page table format. The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new proc-v7-3level.S file contains the TTB initialisation, context switch and PTE setting code with the LPAE. The TTBRx split is based on the PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings (supersections) and a few other memory types in mmu.c are conditionally compiled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: Page table maintenance for the 3-level formatCatalin Marinas5-7/+150
This patch modifies the pgd/pmd/pte manipulation functions to support the 3-level page table format. Since there is no need for an 'ext' argument to cpu_set_pte_ext(), this patch conditionally defines a different prototype for this function when CONFIG_ARM_LPAE. The patch also introduces the L_PGD_SWAPPER flag to mark pgd entries pointing to pmd tables pre-allocated in the swapper_pg_dir and avoid trying to free them at run-time. This flag is 0 with the classic page table format. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: Introduce the 3-level page table format definitionsCatalin Marinas6-0/+261
This patch introduces the pgtable-3level*.h files with definitions specific to the LPAE page table format (3 levels of page tables). Each table is 4KB and has 512 64-bit entries. An entry can point to a 40-bit physical address. The young, write and exec software bits share the corresponding hardware bits (negated). Other software bits use spare bits in the PTE. The patch also changes some variable types from unsigned long or int to pteval_t or pgprot_t. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: add ISBs around MMU enabling codeWill Deacon4-0/+16
Before we enable the MMU, we must ensure that the TTBR registers contain sane values. After the MMU has been enabled, we jump to the *virtual* address of the following function, so we also need to ensure that the SCTLR write has taken effect. This patch adds ISB instructions around the SCTLR write to ensure the visibility of the above. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.SCatalin Marinas2-149/+174
This patch modifies the proc-v7.S file so that it only contains code shared between classic MMU and LPAE. The non-common code is factored out into a separate file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: Move the FSR definitions to separate filesCatalin Marinas3-93/+100
The FSR structure is different with LPAE and this patch moves the classic MMU specific definition to a separate fsr-2level.c file that is included in fault.c. It also moves the fsr_fs and FSR bits to the fault.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: LPAE: Move page table maintenance macros to pgtable-2level.hCatalin Marinas2-38/+41
The page table maintenance macros need to be duplicated between the classic and the LPAE MMU so this patch moves those that are not common to the pgtable-2level.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: pgtable: switch to use pgtable-nopud.hRussell King3-11/+15
Nick Piggin noted upon introducing 4level-fixup.h: | Add a temporary "fallback" header so architectures can run with | the 4level pagetables patch without modification. All architectures | should be converted to use the folding headers (include/asm-generic/ | pgtable-nop?d.h) as soon as possible, and the fallback header removed. This makes ARM compliant with this statement. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: pgtable: Fix compiler warning in ioremap.c introduced by nopudCatalin Marinas1-12/+19
With the arch/arm code conversion to pgtable-nopud.h, the section and supersection (un|re)map code triggers compiler warnings on UP systems. This is caused by pmd_offset() being given a pgd_t argument rather than a pud_t one. This patch makes the necessary conversion with the assumption that the pud is folded into the pgd. The page table setting code only loops over the pmd which is enough with the classic page tables. This code is not compiled when LPAE is enabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08ARM: sa1100: fix build errorJett.Zhou1-2/+2
arm-eabi-4.4.3-ld:--defsym zreladdr=: syntax error make[2]: *** [arch/arm/boot/compressed/vmlinux] Error 1 make[1]: *** [arch/arm/boot/compressed/vmlinux] Error 2 make: *** [uImage] Error 2 Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Jett.Zhou <jtzhou@marvell.com>
2011-12-07arm/tegra: Remove code that's ifndef CONFIG_ARM_GICStephen Warren1-23/+0
entry-macro.S contains some stale code for chips before Tegra20 that apparently didn't use an ARM GIC. All chips supported by mainline use an ARM GIC, so rip out the stale code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2011-12-07arm/tegra: remove unused definespdeschrijver@nvidia.com1-4/+0
PPI_NR is never used in arch/arm/mach-tegra/irq.c. Remove it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2011-12-07arm/tegra: fix variable formatting in makefileOlof Johansson1-13/+13
For some reason it started out using {} instead of (), and it's proliferated from there. Switch back to (). Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Colin Cross <ccross@android.com>
2011-12-07Merge branch 'fixes' of ↵Olof Johansson2-7/+10
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
2011-12-07Merge branch 'samsung-fixes-2' of ↵Arnd Bergmann3-2/+3
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
2011-12-06Merge branch 'kexec/idmap' of ↵Russell King32-89/+140
git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into devel-stable
2011-12-06ARM: 7194/1: OMAP: Fix build after a merge between v3.2-rc4 and ARM restart ↵Tony Lindgren1-1/+2
changes ARM restart changes needed changes to common.h to make it local. This conflicted with v3.2-rc4 DSS related hwmod changes that git mergetool was not able to handle. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-12-06Merge branch 'fixes' of git://gitorious.org/linux-davinci/linux-davinci into ↵Arnd Bergmann6-16/+18
fixes
2011-12-06Merge branch 'mxs/fixes' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Arnd Bergmann5-6/+7
into fixes
2011-12-06Merge branch 'fixes' of ↵Arnd Bergmann2-0/+2
git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel into fixes
2011-12-06Merge branch 'imx/fix-irqdomain' of ↵Arnd Bergmann3-14/+19
git://git.linaro.org/people/shawnguo/linux-2.6 into fixes
2011-12-06Merge branch 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixesArnd Bergmann6-8/+8
2011-12-06ARM: SMP: use idmap_pgd for mapping MMU enable during secondary bootingWill Deacon4-66/+6
The ARM SMP booting code allocates a temporary set of page tables containing an identity mapping of the kernel image and provides this to secondary CPUs for initial booting. In reality, we only need to include the __turn_mmu_on function in the identity mapping since the rest of the kernel is executing from virtual addresses after this point. This patch adds __turn_mmu_on to the .idmap.text section, allowing the SMP booting code to use the idmap_pgd directly and not have to populate its own set of page table. As a result of this patch, we can make the identity_mapping_add function static (since it is only used within mm/idmap.c) and also remove the identity_mapping_del function. The identity map population is moved to an early initcall so that it is setup in time for secondary CPU bringup. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-12-06ARM: head.S: only include __turn_mmu_on in the initial identity mappingWill Deacon1-7/+7
__create_page_tables identity maps the region of memory from __enable_mmu to the end of __turn_mmu_on. In preparation for including __turn_mmu_on in the .idmap.text section, this patch modifies the identity mapping so that it only includes the __turn_mmu_on code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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