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authorSeungwon Jeon <tgih.jun@samsung.com>2014-03-14 21:11:56 +0900
committerStephane Desneux <stephane.desneux@open.eurogiciel.org>2015-02-04 11:14:30 +0100
commitc0bec38bb3d859f432dbec7f65aff93dc666d2b7 (patch)
treee5c353ad8886a415a3d38fe145485932961594d1 /include
parent6b2e24143cf08f8cc43d3ff256601b391fa9ca1a (diff)
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mmc: clarify DDR timing mode between SD-UHS and eMMC
This change distinguishes DDR timing mode of current mixed usage to clarify device type. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net> (cherry picked from commit 79f7ae7c45a6ccf04e2908337461dee615f6afb0) Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mmc/host.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 99f5709ac343..87b1f4f2fe79 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -58,7 +58,8 @@ struct mmc_ios {
#define MMC_TIMING_UHS_SDR50 5
#define MMC_TIMING_UHS_SDR104 6
#define MMC_TIMING_UHS_DDR50 7
-#define MMC_TIMING_MMC_HS200 8
+#define MMC_TIMING_MMC_DDR52 8
+#define MMC_TIMING_MMC_HS200 9
#define MMC_SDR_MODE 0
#define MMC_1_2V_DDR_MODE 1