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| author | Guennadi Liakhovetski <g.liakhovetski@gmx.de> | 2013-12-14 16:23:51 +0100 |
|---|---|---|
| committer | Stephane Desneux <stephane.desneux@open.eurogiciel.org> | 2015-02-04 11:12:55 +0100 |
| commit | 7a84a6374a6097f1f73a7d10c8f5e86d96a7a08d (patch) | |
| tree | 52d633454dedc794e9500fa871ac485b51bc4ed1 /include/linux/sh_clk.h | |
| parent | 4b0649c3d73acc4f40dcd9a6dd503f041672f385 (diff) | |
| download | kernel-common-7a84a6374a6097f1f73a7d10c8f5e86d96a7a08d.tar.gz kernel-common-7a84a6374a6097f1f73a7d10c8f5e86d96a7a08d.tar.bz2 kernel-common-7a84a6374a6097f1f73a7d10c8f5e86d96a7a08d.zip | |
ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
On r-/sh-mobile SoCs MSTP clocks are used by the runtime PM to dynamically
enable and disable peripheral clocks. To make sure the clock has really
started we have to read back its status register until it confirms success.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit a028c6da34d434e35ba8322568c756ea97ff3c18)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'include/linux/sh_clk.h')
| -rw-r--r-- | include/linux/sh_clk.h | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h index 60c72395ec6b..1f208b2a1ed6 100644 --- a/include/linux/sh_clk.h +++ b/include/linux/sh_clk.h @@ -52,6 +52,7 @@ struct clk { unsigned long flags; void __iomem *enable_reg; + void __iomem *status_reg; unsigned int enable_bit; void __iomem *mapped_reg; @@ -116,22 +117,26 @@ long clk_round_parent(struct clk *clk, unsigned long target, unsigned long *best_freq, unsigned long *parent_freq, unsigned int div_min, unsigned int div_max); -#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \ +#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ { \ .parent = _parent, \ .enable_reg = (void __iomem *)_enable_reg, \ .enable_bit = _enable_bit, \ + .status_reg = _status_reg, \ .flags = _flags, \ } -#define SH_CLK_MSTP32(_p, _r, _b, _f) \ - SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT) +#define SH_CLK_MSTP32(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT) -#define SH_CLK_MSTP16(_p, _r, _b, _f) \ - SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT) +#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \ + SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT) -#define SH_CLK_MSTP8(_p, _r, _b, _f) \ - SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT) +#define SH_CLK_MSTP16(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT) + +#define SH_CLK_MSTP8(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT) int sh_clk_mstp_register(struct clk *clks, int nr); |