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| author | Arnd Bergmann <arnd@arndb.de> | 2013-04-09 22:24:06 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2013-04-09 22:28:45 +0200 |
| commit | 19ce4f4a03e52bc694dc837a4a832111cb4271b3 (patch) | |
| tree | 79757bb645e035166ca012373992e185f8d07081 /drivers/clocksource/exynos_mct.c | |
| parent | 228e3023eb0430b4b9ed0736f8f87c96a6cd9c7a (diff) | |
| parent | da821eb7d42935b0f7056d98c75fd1150f6636f4 (diff) | |
| download | kernel-common-19ce4f4a03e52bc694dc837a4a832111cb4271b3.tar.gz kernel-common-19ce4f4a03e52bc694dc837a4a832111cb4271b3.tar.bz2 kernel-common-19ce4f4a03e52bc694dc837a4a832111cb4271b3.zip | |
Merge tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
add suppport common clock framework for exynos
* tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (73 commits)
ARM: EXYNOS: fix compilation error introduced due to common clock migration
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
clk: exynos4: export clocks required for fimc-is
clk: samsung: Fix compilation error
clk: exynos5250: register display block gate clocks to common clock framework
clk: exynos4: Add support for SoC-specific register save list
clk: exynos4: Add missing registers to suspend save list
clk: exynos4: Remove E4X12 prefix from SRC_DMC register
clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register
clk: exynos4: Add E4210 prefix to LCD1 clock registers
clk: exynos4: Remove SoC-specific registers from save list
clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions
clk: exynos4: Define {E,V}PLL registers
clk: exynos4: Add missing mout_sata on Exynos4210
clk: exynos4: Add missing CMU_TOP and ISP clocks
clk: exynos4: Add G3D clocks
clk: exynos4: Add camera related clock definitions
clk: exynos4: Export mout_core clock of Exynos4210
clk: samsung: Remove unimplemented ops for pll
clk: exynos4: Export clocks used by exynos cpufreq drivers
...
[arnd: add missing #address-cells property in mshc DT node]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/clocksource/exynos_mct.c')
| -rw-r--r-- | drivers/clocksource/exynos_mct.c | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 957af8636c9d..509a6019c96c 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -477,12 +477,20 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { }; #endif /* CONFIG_LOCAL_TIMERS */ -static void __init exynos4_timer_resources(void __iomem *base) +static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base) { - struct clk *mct_clk; - mct_clk = clk_get(NULL, "xtal"); + struct clk *mct_clk, *tick_clk; - clk_rate = clk_get_rate(mct_clk); + tick_clk = np ? of_clk_get_by_name(np, "fin_pll") : + clk_get(NULL, "fin_pll"); + if (IS_ERR(tick_clk)) + panic("%s: unable to determine tick clock rate\n", __func__); + clk_rate = clk_get_rate(tick_clk); + + mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct"); + if (IS_ERR(mct_clk)) + panic("%s: unable to retrieve mct clock instance\n", __func__); + clk_prepare_enable(mct_clk); reg_base = base; if (!reg_base) @@ -514,7 +522,7 @@ void __init mct_init(void) panic("unable to determine mct controller type\n"); } - exynos4_timer_resources(S5P_VA_SYSTIMER); + exynos4_timer_resources(NULL, S5P_VA_SYSTIMER); exynos4_clocksource_init(); exynos4_clockevent_init(); } @@ -537,7 +545,7 @@ static void __init mct_init_dt(struct device_node *np, unsigned int int_type) for (i = MCT_L0_IRQ; i < nr_irqs; i++) mct_irqs[i] = irq_of_parse_and_map(np, i); - exynos4_timer_resources(of_iomap(np, 0)); + exynos4_timer_resources(np, of_iomap(np, 0)); exynos4_clocksource_init(); exynos4_clockevent_init(); } |