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| author | Keith Packard <keithp@keithp.com> | 2011-07-22 13:40:42 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-07-22 13:40:42 -0700 |
| commit | df7976797fa9af161690dbf4dee81ed92cdc150f (patch) | |
| tree | be6f04706d91cc80da4dbd3a5f5f2a174f1bdae3 /arch/arm/mach-davinci/gpio.c | |
| parent | f0b69efc29b024747a88ce020dada425e3193d5a (diff) | |
| parent | 9c54c0dd948d715ccfd79e97d852f80eeb53254a (diff) | |
| download | kernel-common-df7976797fa9af161690dbf4dee81ed92cdc150f.tar.gz kernel-common-df7976797fa9af161690dbf4dee81ed92cdc150f.tar.bz2 kernel-common-df7976797fa9af161690dbf4dee81ed92cdc150f.zip | |
Merge branch 'drm-intel-fixes' into drm-intel-next
Diffstat (limited to 'arch/arm/mach-davinci/gpio.c')
| -rw-r--r-- | arch/arm/mach-davinci/gpio.c | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index e7221398e5af..cafbe13a82a5 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -254,8 +254,10 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) { struct davinci_gpio_regs __iomem *g; u32 mask = 0xffff; + struct davinci_gpio_controller *d; - g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc); + d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); + g = (struct davinci_gpio_regs __iomem *)d->regs; /* we only care about one bank */ if (irq & 1) @@ -274,11 +276,14 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) if (!status) break; __raw_writel(status, &g->intstat); - if (irq & 1) - status >>= 16; /* now demux them to the right lowlevel handler */ - n = (int)irq_get_handler_data(irq); + n = d->irq_base; + if (irq & 1) { + n += 16; + status >>= 16; + } + while (status) { res = ffs(status); n += res; @@ -424,7 +429,13 @@ static int __init davinci_gpio_irq_setup(void) /* set up all irqs in this bank */ irq_set_chained_handler(bank_irq, gpio_irq_handler); - irq_set_handler_data(bank_irq, (__force void *)g); + + /* + * Each chip handles 32 gpios, and each irq bank consists of 16 + * gpio irqs. Pass the irq bank's corresponding controller to + * the chained irq handler. + */ + irq_set_handler_data(bank_irq, &chips[gpio / 32]); for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { irq_set_chip(irq, &gpio_irqchip); |