diff options
author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2012-10-30 00:09:18 -0700 |
---|---|---|
committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2012-10-30 00:09:18 -0700 |
commit | 68fe0f0a6dcd2ac1ace5da3647a6d1cf0f4d2fea (patch) | |
tree | 69d855c2e46d42ef8f23680cf3a1e6ff38de9ef4 /Documentation/devicetree/bindings/arm/msm/timer.txt | |
parent | 88fd449e734a4264347e12b8ff74ccb33a9b9a35 (diff) | |
parent | 8f0d8163b50e01f398b14bcd4dc039ac5ab18d64 (diff) | |
download | kernel-common-68fe0f0a6dcd2ac1ace5da3647a6d1cf0f4d2fea.tar.gz kernel-common-68fe0f0a6dcd2ac1ace5da3647a6d1cf0f4d2fea.tar.bz2 kernel-common-68fe0f0a6dcd2ac1ace5da3647a6d1cf0f4d2fea.zip |
Merge tag 'v3.7-rc3' into for-linus to sync up with recent USB changes
Diffstat (limited to 'Documentation/devicetree/bindings/arm/msm/timer.txt')
-rw-r--r-- | Documentation/devicetree/bindings/arm/msm/timer.txt | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt new file mode 100644 index 000000000000..8c5907b9cae8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/timer.txt @@ -0,0 +1,38 @@ +* MSM Timer + +Properties: + +- compatible : Should at least contain "qcom,msm-timer". More specific + properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general + purpose timer and a debug timer respectively. + +- interrupts : Interrupt indicating a match event. + +- reg : Specifies the base address of the timer registers. The second region + specifies an optional register used to configure the clock divider. + +- clock-frequency : The frequency of the timer in Hz. + +Optional: + +- cpu-offset : per-cpu offset used when the timer is accessed without the + CPU remapping facilities. The offset is cpu-offset * cpu-nr. + +Example: + + timer@200a004 { + compatible = "qcom,msm-gpt", "qcom,msm-timer"; + interrupts = <1 2 0x301>; + reg = <0x0200a004 0x10>; + clock-frequency = <32768>; + cpu-offset = <0x40000>; + }; + + timer@200a024 { + compatible = "qcom,msm-dgt", "qcom,msm-timer"; + interrupts = <1 3 0x301>; + reg = <0x0200a024 0x10>, + <0x0200a034 0x4>; + clock-frequency = <6750000>; + cpu-offset = <0x40000>; + }; |