diff options
| -rw-r--r-- | src/intel.h | 1 | ||||
| -rw-r--r-- | src/intel_driver.c | 22 | ||||
| -rw-r--r-- | src/intel_shadow.c | 4 |
3 files changed, 20 insertions, 7 deletions
diff --git a/src/intel.h b/src/intel.h index fa79a2f98..ed21b1e8a 100644 --- a/src/intel.h +++ b/src/intel.h @@ -443,6 +443,7 @@ typedef struct intel_screen_private { Bool use_pageflipping; Bool force_fallback; + Bool can_blt; Bool use_shadow; /* Broken-out options. */ diff --git a/src/intel_driver.c b/src/intel_driver.c index 926c7e31a..e4aecfcfd 100644 --- a/src/intel_driver.c +++ b/src/intel_driver.c @@ -468,8 +468,21 @@ static void I830XvInit(ScrnInfoPtr scrn) intel->colorKey); } -static Bool can_accelerate_2d(struct intel_screen_private *intel) +static Bool can_accelerate_blt(struct intel_screen_private *intel) { + if (IS_I830(intel) || IS_845G(intel)) { + /* These pair of i8xx chipsets have a crippling erratum + * that prevents the use of a PTE entry by the BLT + * engine immediately following updating that + * entry in the GATT. + * + * As the BLT is fundamental to our 2D acceleration, + * and the workaround is lost in the midst of time, + * fallback. + */ + return FALSE; + } + if (INTEL_INFO(intel)->gen >= 60) { drm_i915_getparam_t gp; int value; @@ -592,9 +605,8 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags) intel->tiling = FALSE; } - intel->use_shadow = FALSE; - if (!can_accelerate_2d(intel)) - intel->use_shadow = TRUE; + intel->can_blt = can_accelerate_blt(intel); + intel->use_shadow = !intel->can_blt; if (xf86IsOptionSet(intel->Options, OPTION_SHADOW)) { intel->use_shadow = @@ -606,7 +618,7 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags) if (intel->use_shadow) { xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "Shadow buffer enabled," - " GPU acceleration disabled.\n"); + " 2D GPU acceleration disabled.\n"); } /* SwapBuffers delays to avoid tearing */ diff --git a/src/intel_shadow.c b/src/intel_shadow.c index c12febc4b..b86530a9c 100644 --- a/src/intel_shadow.c +++ b/src/intel_shadow.c @@ -108,7 +108,7 @@ void intel_shadow_blt(intel_screen_private *intel) int n; /* Can we trust the BLT? Otherwise do an uncached mmecy. */ - if (IS_GEN2(intel) || IS_GEN6(intel)) { + if (!intel->can_blt || IS_GEN2(intel)) { intel_shadow_memcpy(intel); return; } @@ -149,7 +149,7 @@ void intel_shadow_blt(intel_screen_private *intel) if (bo == NULL) return; - BEGIN_BATCH(8); + BEGIN_BATCH_BLT(8); OUT_BATCH(blt); OUT_BATCH(br13); OUT_BATCH(box->y1 << 16 | box->x1); |