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authorWang Zhenyu <zhenyu.z.wang@intel.com>2006-08-24 10:23:22 +0800
committerWang Zhenyu <zhenyu.z.wang@intel.com>2006-08-24 10:23:22 +0800
commit078af29fa65653c5322b006404f7ad29aec24cce (patch)
tree1c05fbbbc4e07cb6f2e930bc6048f8fa288a38f1 /src/i830_accel.c
parent7458a6adb5ea62f56bb3d4ab19ad7d1aa6ad2d19 (diff)
parentea63e82ef417a9918e7d7105910a8ddeba2994f6 (diff)
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Merge branch 'master' into exa
Conflicts: man/i810.man src/Makefile.am src/i830_accel.c src/i830_dga.c src/i830_driver.c
Diffstat (limited to 'src/i830_accel.c')
-rw-r--r--src/i830_accel.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/i830_accel.c b/src/i830_accel.c
index 6b3388797..6ad62d1f0 100644
--- a/src/i830_accel.c
+++ b/src/i830_accel.c
@@ -134,6 +134,7 @@ void
I830Sync(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
+ int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
ErrorF("I830Sync\n");
@@ -148,13 +149,17 @@ I830Sync(ScrnInfoPtr pScrn)
if (pI830->entityPrivate && !pI830->entityPrivate->RingRunning) return;
+ if (IS_I965G(pI830))
+ flags = 0;
+
/* Send a flush instruction and then wait till the ring is empty.
* This is stronger than waiting for the blitter to finish as it also
* flushes the internal graphics caches.
*/
+
{
BEGIN_LP_RING(2);
- OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
+ OUT_RING(MI_FLUSH | flags);
OUT_RING(MI_NOOP); /* pad to quadword */
ADVANCE_LP_RING();
}
@@ -169,9 +174,13 @@ void
I830EmitFlush(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
+ int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
+
+ if (IS_I965G(pI830))
+ flags = 0;
BEGIN_LP_RING(2);
- OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
+ OUT_RING(MI_FLUSH | flags);
OUT_RING(MI_NOOP); /* pad to quadword */
ADVANCE_LP_RING();
}
@@ -233,4 +242,3 @@ I830AccelInit(ScreenPtr pScreen)
#endif
return FALSE;
}
-