diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2009-06-05 11:57:57 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2009-06-10 10:24:51 +0800 |
| commit | 4f40b33ef4b069b18a6a18406da83a23ca6e1127 (patch) | |
| tree | 157371b99422bc1ed26e904fe978212b0e88e9b1 /src/common.h | |
| parent | accdbd23676d812d2345f86d8e3ee62f108841ff (diff) | |
| download | xf86-video-intel-4f40b33ef4b069b18a6a18406da83a23ca6e1127.tar.gz xf86-video-intel-4f40b33ef4b069b18a6a18406da83a23ca6e1127.tar.bz2 xf86-video-intel-4f40b33ef4b069b18a6a18406da83a23ca6e1127.zip | |
Add new chipsets PCI ids
Desktop and mobile version of new chipsets are added.
Also do memory config like Intel 4 series chipset.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'src/common.h')
| -rw-r--r-- | src/common.h | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/src/common.h b/src/common.h index 335fe75f3..69f560410 100644 --- a/src/common.h +++ b/src/common.h @@ -310,6 +310,16 @@ extern int I810_DEBUG; #define PCI_CHIP_G41_G_BRIDGE 0x2E30 #endif +#ifndef PCI_CHIP_IGDNG_D_G +#define PCI_CHIP_IGDNG_D_G 0x0042 +#define PCI_CHIP_IGDNG_D_G_BRIDGE 0x0040 +#endif + +#ifndef PCI_CHIP_IGDNG_M_G +#define PCI_CHIP_IGDNG_M_G 0x0046 +#define PCI_CHIP_IGDNG_M_G_BRIDGE 0x0044 +#endif + #define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr #define VENDOR_ID(p) (p)->vendor_id #define DEVICE_ID(p) (p)->device_id @@ -339,7 +349,10 @@ extern int I810_DEBUG; #define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || IS_GM45(pI810)) #define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME) #define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q) -#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810)) +#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G) +#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G) +#define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810)) +#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810) || IS_IGDNG(pI810)) #define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\ DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\ DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \ @@ -347,20 +360,20 @@ extern int I810_DEBUG; #define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810)) #define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810)) -#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810)) +#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810)) /* mark chipsets for using gfx VM offset for overlay */ #define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810)) /* mark chipsets without overlay hw */ -#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810)) +#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) /* chipsets require graphics mem for hardware status page */ #define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \ (IS_G33CLASS(pI810) ||\ - IS_G4X(pI810))) + IS_G4X(pI810) || IS_IGDNG(pI810))) /* chipsets require status page in non stolen memory */ -#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810)) -#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810)) +#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) +#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) /* dsparb controlled by hw only */ -#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810)) +#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) /* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ #define SUPPORTS_YTILING(pI810) (IS_I965G(pI830)) |