summaryrefslogtreecommitdiff
path: root/common_mips64.h
AgeCommit message (Collapse)AuthorFilesLines
2013-04-11Fixed the SEGFAULT bug with Loongcc and Loongson3.Xianyi Zhang1-2/+2
2011-12-01Adding n32 multiple threads condition.Wang Qian1-0/+2
2011-11-17Disable using simple thread level3 to fix a bug on Loongson 3B.Xianyi Zhang1-4/+5
2011-11-11Enable thread affinity on Loongson 3B. Fixed the bug of reading cycle counter.Xianyi Zhang1-7/+21
In Loongson 3A and 3B, the CPU core increases the counter in every 2 cycles by default.
2011-11-09Support detecting ICT Loongson-3B CPU.Xianyi Zhang1-2/+10
2011-09-15Complete cgemm function, but no optimization.traz1-0/+2
2011-08-30Modify compile options.traz1-1/+8
2011-04-11Changed default page size to 16KB on Loongson 3A.Xianyi Zhang1-0/+5
2011-01-26added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch ↵Xianyi Zhang1-0/+8
distance & instruction order.
2011-01-25Modified the unsupported instruction on Loongson3A. Closed #1 OpenBLAS could ↵Xianyi Zhang1-2/+38
run on Loongson3A now.
2011-01-24Import GotoBLAS2 1.13 BSD version codes.Xianyi Zhang1-0/+197