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authorShivraj Patil <shivraj.patil@imgtec.com>2017-09-22 11:57:43 +0530
committerShivraj Patil <shivraj.patil@imgtec.com>2017-09-22 11:57:43 +0530
commite3d844b0621fc0d6849626e580581507366055c7 (patch)
tree381b61c6c54d57632fe6da041efdf3a6e41f6811 /cpuid_mips64.c
parentdef146efed8d5908ea04e22668feeab7099599a0 (diff)
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Added mips I6500 core
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
Diffstat (limited to 'cpuid_mips64.c')
-rw-r--r--cpuid_mips64.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/cpuid_mips64.c b/cpuid_mips64.c
index ac1554c79..dcb559a7c 100644
--- a/cpuid_mips64.c
+++ b/cpuid_mips64.c
@@ -76,6 +76,7 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define CPU_LOONGSON3B 3
#define CPU_I6400 4
#define CPU_P6600 5
+#define CPU_I6500 6
static char *cpuname[] = {
"UNKOWN",
@@ -83,7 +84,8 @@ static char *cpuname[] = {
"LOONGSON3A",
"LOONGSON3B",
"I6400",
- "P6600"
+ "P6600",
+ "I6500"
};
int detect(void){
@@ -165,6 +167,8 @@ void get_subarchitecture(void){
printf("I6400");
}else if(detect()==CPU_P6600){
printf("P6600");
+ }else if(detect()==CPU_I6500){
+ printf("I6500");
}else{
printf("SICORTEX");
}
@@ -211,6 +215,15 @@ void get_cpuconfig(void){
printf("#define DTB_DEFAULT_ENTRIES 64\n");
printf("#define DTB_SIZE 4096\n");
printf("#define L2_ASSOCIATIVE 8\n");
+ }else if(detect()==CPU_I6500){
+ printf("#define I6500\n");
+ printf("#define L1_DATA_SIZE 65536\n");
+ printf("#define L1_DATA_LINESIZE 32\n");
+ printf("#define L2_SIZE 1048576\n");
+ printf("#define L2_LINESIZE 32\n");
+ printf("#define DTB_DEFAULT_ENTRIES 64\n");
+ printf("#define DTB_SIZE 4096\n");
+ printf("#define L2_ASSOCIATIVE 8\n");
}else{
printf("#define SICORTEX\n");
printf("#define L1_DATA_SIZE 32768\n");
@@ -232,6 +245,8 @@ void get_libname(void){
printf("i6400\n");
}else if(detect()==CPU_P6600) {
printf("p6600\n");
+ }else if(detect()==CPU_I6500) {
+ printf("i6500\n");
}else{
printf("mips64\n");
}