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| author | Xianyi Zhang <xianyi@iscas.ac.cn> | 2012-03-30 20:01:03 +0800 |
|---|---|---|
| committer | Xianyi Zhang <xianyi@iscas.ac.cn> | 2012-03-30 20:01:03 +0800 |
| commit | 19a48b82cf3c4aa25659ea89dce494e2d78fed25 (patch) | |
| tree | 0b2a054bdc43af6af73815a3828668757e7f3b4e /cpuid.h | |
| parent | 5cbbc496b0eba5eb31505aa5746d1152bb04746e (diff) | |
| download | openblas-19a48b82cf3c4aa25659ea89dce494e2d78fed25.tar.gz openblas-19a48b82cf3c4aa25659ea89dce494e2d78fed25.tar.bz2 openblas-19a48b82cf3c4aa25659ea89dce494e2d78fed25.zip | |
Init Sandybridge codes based on Nehalem.
Diffstat (limited to 'cpuid.h')
| -rw-r--r-- | cpuid.h | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -103,6 +103,7 @@ #define CORE_NEHALEM 17 #define CORE_ATOM 18 #define CORE_NANO 19 +#define CORE_SANDYBRIDGE 20 #define HAVE_SSE (1 << 0) #define HAVE_SSE2 (1 << 1) @@ -122,6 +123,7 @@ #define HAVE_MISALIGNSSE (1 << 15) #define HAVE_128BITFPU (1 << 16) #define HAVE_FASTMOVU (1 << 17) +#define HAVE_AVX (1 << 18) #define CACHE_INFO_L1_I 1 #define CACHE_INFO_L1_D 2 @@ -188,4 +190,5 @@ typedef struct { #define CPUTYPE_NSGEODE 41 #define CPUTYPE_VIAC3 42 #define CPUTYPE_NANO 43 +#define CPUTYPE_SANDYBRIDGE 44 #endif |