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| author | Xianyi Zhang <xianyi@iscas.ac.cn> | 2011-01-26 22:34:33 +0800 |
|---|---|---|
| committer | Xianyi Zhang <xianyi@iscas.ac.cn> | 2011-01-26 22:34:33 +0800 |
| commit | c0b5992fab289b6c5dcf1f4335f9db9ccd5ea0ab (patch) | |
| tree | 807583e1a649051d3d4cf12e2beac9044552c28b /common_mips64.h | |
| parent | 376677452fee8571f937d688a5489cd1cf44dff6 (diff) | |
| download | openblas-c0b5992fab289b6c5dcf1f4335f9db9ccd5ea0ab.tar.gz openblas-c0b5992fab289b6c5dcf1f4335f9db9ccd5ea0ab.tar.bz2 openblas-c0b5992fab289b6c5dcf1f4335f9db9ccd5ea0ab.zip | |
added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order.
Diffstat (limited to 'common_mips64.h')
| -rw-r--r-- | common_mips64.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/common_mips64.h b/common_mips64.h index 5745dec6b..7c7a70ba5 100644 --- a/common_mips64.h +++ b/common_mips64.h @@ -230,4 +230,12 @@ REALNAME: ;\ #ifndef MAP_ANONYMOUS #define MAP_ANONYMOUS MAP_ANON #endif + +#if defined(LOONGSON3A) +#define PREFETCHD_(x) ld $0, x +#define PREFETCHD(x) PREFETCHD_(x) +#else +#define PREFETCHD(x) +#endif + #endif |