1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
|
#ifndef NASM_IFLAG_H
#define NASM_IFLAG_H
#include <inttypes.h>
#include <string.h>
#include "compiler.h"
int ilog2_32(uint32_t v);
/*
* Instruction template flags. These specify which processor
* targets the instruction is eligible for, whether it is
* privileged or undocumented, and also specify extra error
* checking on the matching of the instruction.
*
* IF_SM stands for Size Match: any operand whose size is not
* explicitly specified by the template is `really' intended to be
* the same size as the first size-specified operand.
* Non-specification is tolerated in the input instruction, but
* _wrong_ specification is not.
*
* IF_SM2 invokes Size Match on only the first _two_ operands, for
* three-operand instructions such as SHLD: it implies that the
* first two operands must match in size, but that the third is
* required to be _unspecified_.
*
* IF_SB invokes Size Byte: operands with unspecified size in the
* template are really bytes, and so no non-byte specification in
* the input instruction will be tolerated. IF_SW similarly invokes
* Size Word, and IF_SD invokes Size Doubleword.
*
* (The default state if neither IF_SM nor IF_SM2 is specified is
* that any operand with unspecified size in the template is
* required to have unspecified size in the instruction too...)
*
* iflag_t is defined to store these flags.
*/
#include "iflaggen.h"
#define IF_GENBIT(bit) (UINT32_C(1) << (bit))
static inline unsigned int iflag_test(iflag_t *f,unsigned int bit)
{
unsigned int index = bit / 32;
return f->field[index] & (UINT32_C(1) << (bit - (index * 32)));
}
static inline void iflag_set(iflag_t *f, unsigned int bit)
{
unsigned int index = bit / 32;
f->field[index] |= (UINT32_C(1) << (bit - (index * 32)));
}
static inline void iflag_clear(iflag_t *f, unsigned int bit)
{
unsigned int index = bit / 32;
f->field[index] &= ~(UINT32_C(1) << (bit - (index * 32)));
}
static inline void iflag_clear_all(iflag_t *f)
{
memset(f, 0, sizeof(*f));
}
static inline void iflag_set_all(iflag_t *f)
{
memset(f, 0xff, sizeof(*f));
}
static inline int iflag_cmp(iflag_t *a, iflag_t *b)
{
unsigned int i;
for (i = 0; i < sizeof(a->field) / sizeof(a->field[0]); i++) {
if (a->field[i] < b->field[i])
return -1;
else if (a->field[i] > b->field[i])
return 1;
}
return 0;
}
static inline int iflag_cmp_cpu(iflag_t *a, iflag_t *b)
{
if (a->field[3] < b->field[3])
return -1;
else if (a->field[3] > b->field[3])
return 1;
return 0;
}
static inline unsigned int iflag_ffs(iflag_t *a)
{
unsigned int i;
for (i = 0; i < sizeof(a->field) / sizeof(a->field[0]); i++) {
if (a->field[i])
return ilog2_32(a->field[i]) + (i * 32);
}
return 0;
}
#define IF_GEN_HELPER(name, op) \
static inline iflag_t iflag_##name(iflag_t *a, iflag_t *b) \
{ \
unsigned int i; \
iflag_t res; \
\
for (i = 0; i < sizeof(a->field) / sizeof(a->field[0]); i++) \
res.field[i] = a->field[i] op b->field[i]; \
\
return res; \
}
IF_GEN_HELPER(xor, ^)
/* Use this helper to test instruction template flags */
#define itemp_has(itemp, bit) iflag_test(&insns_flags[(itemp)->iflag_idx], bit)
/* Maximum processor level at moment */
#define IF_PLEVEL IF_IA64
/* Some helpers which are to work with predefined masks */
#define IF_SMASK \
(IF_GENBIT(IF_SB) |\
IF_GENBIT(IF_SW) |\
IF_GENBIT(IF_SD) |\
IF_GENBIT(IF_SQ) |\
IF_GENBIT(IF_SO) |\
IF_GENBIT(IF_SY) |\
IF_GENBIT(IF_SZ) |\
IF_GENBIT(IF_SIZE))
#define IF_ARMASK \
(IF_GENBIT(IF_AR0) |\
IF_GENBIT(IF_AR1) |\
IF_GENBIT(IF_AR2) |\
IF_GENBIT(IF_AR3) |\
IF_GENBIT(IF_AR4))
#define __itemp_smask(idx) (insns_flags[(idx)].field[0] & IF_SMASK)
#define __itemp_armask(idx) (insns_flags[(idx)].field[0] & IF_ARMASK)
#define __itemp_arg(idx) ((__itemp_armask(idx) >> IF_AR0) - 1)
#define itemp_smask(itemp) __itemp_smask((itemp)->iflag_idx)
#define itemp_arg(itemp) __itemp_arg((itemp)->iflag_idx)
#define itemp_armask(itemp) __itemp_armask((itemp)->iflag_idx)
static inline int iflag_cmp_cpu_level(iflag_t *a, iflag_t *b)
{
iflag_t v1 = *a;
iflag_t v2 = *b;
iflag_clear(&v1, IF_CYRIX);
iflag_clear(&v1, IF_AMD);
iflag_clear(&v2, IF_CYRIX);
iflag_clear(&v2, IF_AMD);
if (v1.field[3] < v2.field[3])
return -1;
else if (v1.field[3] > v2.field[3])
return 1;
return 0;
}
static inline iflag_t __iflag_pfmask(iflag_t *a)
{
iflag_t r = (iflag_t) {
.field[1] = a->field[1],
.field[2] = a->field[2],
};
if (iflag_test(a, IF_CYRIX))
iflag_set(&r, IF_CYRIX);
if (iflag_test(a, IF_AMD))
iflag_set(&r, IF_AMD);
return r;
}
#define iflag_pfmask(itemp) __iflag_pfmask(&insns_flags[(itemp)->iflag_idx])
#endif /* NASM_IFLAG_H__ */
|
