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2014-05-21BR 3392279: Fix duplicated REX prefixesH. Peter Anvin1-0/+8
The fix for BR 3392278: aa29b1d93f5a assemble.c: Don't drop rex prefix from instruction itself ... would cause multiple REX prefixes to be emitted for some instructions. Create a new flag to indicate that REX has already been emitted, which can be cleared for each instance of an instruction. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2014-02-16BR 3392275: Don't require xmm0 to be specified when implicitH. Peter Anvin1-0/+12
BR 3392275 complains about xmm0 having to be explicitly included in the assembly syntax when it is implicit in the encoding. In the interest of "be liberal in what you accept", accept either form in the input. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-12-18mpx: Clean up instruction dataJin Kyu Song1-0/+1
Cleaned up unneccessary size specifiers in the instruction data. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-28Add {vex3} and {vex2} prefixes by analogy with {evex}H. Peter Anvin1-0/+9
Allow specifying {vex3} or {vex2} (the latter is currently always redundant, unless we end up with instructions at some point can be specified with legacy prefixes or VEX) to select a specific encoding of VEX-encoded instructions. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-11-27testcase: Remove escape characters - '\'Jin Kyu Song5-4401/+4401
Since the multi-line macro preprocessor is modified to expand grouped parameter with braces. The escape character is not needed any more. The testcase converter script is also modified not to generate '\'. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-22bnd: Drop bnd prefix for relaxed short jmp instructionsJin Kyu Song2-2/+8
Reverted the redundant branch instruction patterns for bnd prefix. And when a relaxed jmp instruction becomes a short (Jb) form, bnd prefix is not needed because it does not initialize bnd registers. So in that case, bnd prefix is silently dropped. BND JMP foo -> drops bnd prefix BND JMP short foo -> shows an explicit error Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Adapt GAS's mib syntax with an index reg onlyJin Kyu Song1-4/+4
GAS uses *1 multiplier for explicitly marking an index register in mib operand. e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format So only for mib operands, this is encoded same as gas does. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20SHA: SHA test casesJin Kyu Song2-0/+61
32bit and 64bit test asm files. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add test cases for MPXJin Kyu Song2-0/+202
MPX test asm files are added. These include all three different styles of mib syntax (NASM, ICC and gas). Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20parser: support split base,index effective addressH. Peter Anvin1-0/+11
Mostly intended for the "mib" expressions in BNDLDX/BNDSTX. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20AVX-512: Add perfomtest-compliant headers to test casesJin Kyu Song4-1/+5
test/avx512*.asm files are now tested by using perfomtest.pl Refer to pefomtest help message for the usage. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-09-14AVX-512: Added AVX-512PF instructionsJin Kyu Song1-0/+87
Added Prefetch (AVX-512PF) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1. CPUID feature flag for PREFETCHWT1 is TBD but PREFETCHWT1 is included in this commit. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-14AVX-512: Add AVX-512ER instructionsJin Kyu Song1-0/+143
Added Exponential and Reciprocal (AVX-512ER) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1. IF_AVX512 is now shared by all AVX-512* instructions as a bit mask. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-14AVX-512: Add AVX-512CD instructionsJin Kyu Song1-0/+105
Added Conflict Detection (AVX-512CD) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512CD[bit 28] = 1. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-07AVX-512: Add Pseudo-ops for CMP instructionsJin Kyu Song2-5/+2381
Added three-operand pseudo-ops for VCMPPD, VPCMPD and so on. Test case is also updated to validate them. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-29AVX-512: Add test case for opmask instructionsJin Kyu Song2-4578/+24
Added K* instructions test cases in test/avx512f.asm. The previous test case from GNU AS were repeating the same instruction twice, so the repeated half part is removed. Changed the python script (gas2nasm.py) to include opmask instructions. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-29AVX-512: Fix commentsJin Kyu Song1-1/+0
Fixed or purged some old comments and added a comment for a previous patch. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-28AVX-512: Add a feature to generate a raw bytecode fileJin Kyu Song1-0/+11
From gas testsuite file, a text file containing raw bytecodes is useful when verifying the output of NASM. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-28AVX-512: Add a test case for EVEX encoded instructionsJin Kyu Song2-0/+9271
This was converted from a gas testsuite. (gas/testsuite/gas/i386/x86-64-avx512f-intel.d) A python script that is used for converting is also included. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-07-21test: Add br978756Cyrill Gorcunov1-0/+7
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-07-21test: Add br3392259Cyrill Gorcunov1-0/+8
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-07-19BR 3392260: Handle instructions only separated by vector SIB sizeH. Peter Anvin1-0/+11
There are two instructions (VGATHERQPS, VPGATHERQD) where the only separation between two forms is the vector length given to the vector SIB. This means the *matcher* has to be able to distinguish instructions by vector SIB length and the matcher only operates on the operands and the instruction flags, not on the bytecode. Export the vector index-ness into the operand flags and add to the matcher. This resolves BR 3392260. Reported-by: Agner <agner@anger.org> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-05-13test: Add br3392252 testCyrill Gorcunov1-0/+43
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2012-07-22hle: opcode A2 forbidden with HLE prefixesH. Peter Anvin1-0/+4
The moffset opcodes A2 and A3 do not support HLE. Unfortunately checkin fb3f4e6d HLE: Change NOHLE to be an instruction flag ... inadvertently lost the NOHLE flag for opcode A2. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-05-31test: ilog2() testH. Peter Anvin1-0/+271
Test for the ilog2 function/macros. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-03-06test: Add br3385573 testcaseCyrill Gorcunov1-0/+11
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2012-03-05Try again to fix our handling of MOVD/MOVQH. Peter Anvin1-0/+15
Try to implement the handling of MOVD as attempted in checkin: 70712c0df6c437c50452c4997aa2e3de5a0e0299 and reverted in: d279fbbd80aab6f79584249629a4aea90b851458 due to BR3392199. This time make sure to use the SX flag to only match when a size is explicitly given, and also don't duplicate the 0F 6F/7F opcodes, which are documented as MOVQ by AMD as well as Intel. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-25HLE: Change NOHLE to be an instruction flagH. Peter Anvin1-0/+15
The way our matching system works we have to make NOHLE an instruction flag rather than an byte code; by the time we run the byte code interpreter we have already picked an instruction pattern once and for all. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-25Add support for UTF-16BE and UTF-32BEH. Peter Anvin1-0/+52
Add support for bigendian UTF-16 and UTF-32, and (for symmetry) add explicitly littleendian operators. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-25Clean up JMP/CALL patterns, especially for 64 bitsH. Peter Anvin1-0/+4
Clean up JMP/CALL patterns so they don't disassemble quite so uglily. Fix a CALL pattern which would have incorrectly generated a (harmless) REX.W prefix. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2011-08-31Add AVX2 test fileCyrill Gorcunov1-0/+1608
nasm64developer kindly provided a testfile converted to nasm format. http://sourceware.org/ml/binutils/2011-06/msg00150.html Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-06-26test: Add movd.asmCyrill Gorcunov1-0/+12
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-06-22Implement the VGATHERP instructionH. Peter Anvin1-0/+76
As an initial test of the VSIB handling, implement the VGATHERP instruction. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-03-12Merge branch 'nasm-2.09.xx'Cyrill Gorcunov2-0/+16
Conflicts: doc/changes.src version Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-03-07test: Add br3189064Cyrill Gorcunov1-0/+7
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-03-07test: Add br3200749Cyrill Gorcunov1-0/+9
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-02-21Merge branch 'nasm-2.09.xx'Cyrill Gorcunov1-0/+7
2011-02-21test: Add test for BR 3187743Cyrill Gorcunov1-0/+7
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-02-14Merge branch 'nasm-2.09.xx'Cyrill Gorcunov1-0/+9
Conflicts: insns.dat Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-02-14test: Add test for BR3174983Cyrill Gorcunov1-0/+9
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2010-12-29Move implicit operand size override logic to calc_sizeVictor van den Elzen2-1/+29
It is more logical, it cleans up the code and it makes implicit operand size override prefixes come out in the same order as explicit ones instead of after all other prefixes. Suggested-by: H. Peter Anvin <hpa@zytor.com>
2010-11-21BR3058845: mostly fix bogus warning with implicit operand size overrideVictor van den Elzen1-0/+14
The implicit operand size override code didn't set the operand size prefix, which confused the size calculation code for the range check. The BITS 64 operand size calculation is still off, but "fixing" it by making it 32-bit unless REX.W is set breaks PUSH and maybe others.
2010-11-16Merge branch 'nasm-2.09.xx'H. Peter Anvin1-0/+9
2010-11-16BR 3109604: Fix C4 vs C5 VEX form selection in calcsize()H. Peter Anvin1-0/+9
calcsize() had the wrong criterion for when C5 prefixes are permitted (REX.R is permitted, REX.X is forbidden.) assemble() had the right test already. This caused symbol value errors.
2010-11-07BR3058845: mostly fix bogus warning with implicit operand size overrideVictor van den Elzen1-0/+14
The implicit operand size override code didn't set the operand size prefix, which confused the size calculation code for the range check. The BITS 64 operand size calculation is still off, but "fixing" it by making it 32-bit unless REX.W is set breaks PUSH and maybe others.
2010-11-06test: Add br3104312.asm testCyrill Gorcunov1-0/+11
Not automated yet Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2010-11-06test: Add br3092924.asmCyrill Gorcunov1-0/+25
coff massive relocations test Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2010-09-30More tests automationCyrill Gorcunov10-1/+25
Not all covered but still worth to put in Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2010-09-24test: Add br3074517.asmCyrill Gorcunov1-0/+12
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2010-09-18Merge branch 'nasm-2.09.xx'Cyrill Gorcunov1-0/+68
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