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2013-11-27opflags: Separate vector registers into low-16 and high-16Jin Kyu Song1-3/+6
Since only EVEX supports all 32 vector registers encoding for now, VEX/REX encoded instructions should not take high-16 registers as operands. This filtering had been done using instruction flag so far, but using the opflags makes more sense. [XYZ]MMREG operands used for non-EVEX instructions are automatically converted to [XYZ]MM_L16 in insns.pl Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add MPX instructionsJin Kyu Song1-0/+3
Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index As a supplement to NASM style mib - split EA - parser, omitted base+disp is now treated as 0 displacement. E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-08-29AVX-512: Remove trailing space and align columnsJin Kyu Song1-1/+1
Cosmetic change Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-29AVX-512: Fix commentsJin Kyu Song1-1/+1
Fixed or purged some old comments and added a comment for a previous patch. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-16AVX-512: Add EVEX encoding and new instructionsJin Kyu Song1-2/+2
EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM), opmask, broadcasting, embedded rounding mode, suppress all exceptions, compressed displacement. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-06AVX-512: Add support for parsing bracesJin Kyu Song1-1/+14
AVX-512 introduced new syntax using braces for decorators. Opmask, broadcat, rounding control use this new syntax. http://software.intel.com/sites/default/files/319433-015.pdf Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-03-03insns: Remove pushseg/popseg internal bytecodesBen Rudiak-Gould1-5/+5
This patch is getting rid of the following bytecodes 'pushseg','popseg','pushseg2','popseg2' and simplifies overall code. [gorcunov@: a few style fixes] Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2009-06-28Add copyright notices to other *.dat filesH. Peter Anvin1-0/+33
Add copyright notices to the other *.dat files. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2008-05-26Fix register numbers for ymm1-15!H. Peter Anvin1-1/+1
ymm1-15 were incorrectly listed as starting at register number 0, with obviously disastrous consequences...
2008-05-20Add support for ymm0 in instructionsH. Peter Anvin1-1/+2
Make it possible to use ymm0 as a fixed operand in instructions
2008-04-21Initial support for YMM (AVX) registersH. Peter Anvin1-0/+3
Add support for ymm0..15 registers, and the "ymmreg" qualifier. No support yet for "yword" or "dy".
2007-11-12Fix handling of XCHG in 64-bit modeH. Peter Anvin1-24/+24
The handling of XCHG in 64-bit mode somewhat broken. Add a register flag for "not accumulator", so we can generate all the appropriate modes.
2007-09-12Add (untested!) SSSE3, SSE4.1, SSE4.2 instructionsH. Peter Anvin1-1/+2
Add the SSSE3, SSE4.1 and SSE4.2 instruction sets. Change \332 to be a literal 0xF2 prefix, by analog with \333 for 0xF3 prefix (the previous \332 flag changed to \335). This is necessary to get the REX prefix in the right place for instructions that use it. We are going to have to go in and change existing instruction patterns which use these, as well.
2007-09-12Remove $Id$ tags (useless with git)H. Peter Anvin1-1/+0
Remove CVS $Id$ tags, since git doesn't use them.
2007-08-28Implement REL/ABS modifiersH. Peter Anvin1-4/+0
Implement "REL" and "ABS" modifiers for offsets in 64-bit mode. This replaces "rip+XXX" type addressing. The infrastructure to set the default mode is there, but there is nothing to throw the switch just yet.
2007-08-20regs.pl: handle dashed sequences with suffixesH. Peter Anvin1-32/+4
Handle dashed sequences with suffixes. Use that for r8-r15[bwd].
2007-05-30Get rid of magic open-coded "register numbers"H. Peter Anvin1-129/+88
Get rid of magic open-coded register numbers. We now keep track of a total of three different kinds of register numbers: the register enumeration (regs.h), the x86 register value, and the register flags. That has all the information we need. Additionally, do massive revamping of the EA generation code and the REX generation logic.
2007-05-30More cleanup of operand flags/register classesH. Peter Anvin1-4/+4
2007-05-15regs.dat: fix commentH. Peter Anvin1-1/+1
2007-04-16Filled in all RIP Register Flags.Keith Kanios1-1/+1
2007-04-16Use + instead of * for extension; it feels cleaner with the new meaning.H. Peter Anvin1-10/+10
We used to use * to mean substitute in 0-7. Now it means that it should be incremented 8 times. Using a different character feels cleaner.
2007-04-15Clean up the 64-bitification of regs.dat for 64-bit ndisasm supportH. Peter Anvin1-152/+104
64-bit support required some major changes to regs.dat; clean some of it up (re-introduce patterns, where appropriate) and allow a single register to belong to multiple disassembly classes; also keep track of the x86 register number again.
2007-04-15Fix the register number for CR7 (it was using the same number as CR15).H. Peter Anvin1-1/+1
2007-04-12General push for x86-64 support, dubbed 0.99.00.Keith Kanios1-45/+180
2003-02-24Add support for the new instructions in PrescottH. Peter Anvin1-2/+2
2002-06-06This is the "megapatch":H. Peter Anvin1-0/+68
a) Automatically generate dependencies for all Makefiles; b) Move register definitions to a separate .dat file; c) Add support for "unimplemented but there in theory" registers.
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