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bnd and nobnd prifixes can be used for each instruction line to
direct whether bnd registers should be preserved or not.
And those are also added as options for DEFAULT directive.
Once bnd is set with default, DEFAULT BND, all bnd-prefix
available instructions are prefixed with bnd. To override it,
nobnd prefix can be used.
In the other way, DEFAULT NOBND can disable DEFAULT BND and
have nasm encode in the normal way.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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Allow specifying {vex3} or {vex2} (the latter is currently always
redundant, unless we end up with instructions at some point can be
specified with legacy prefixes or VEX) to select a specific encoding
of VEX-encoded instructions.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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As recommended by the community, a comma-separated decorators ({k1,z})
and nested braces ({{k1},{z}}) are dropped out. So only standard syntax
is supported from now.
This rework made source code neat and easy to maintain. Most of the codes
for handling corner cases are removed.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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The broadcasting decorator {1to##} must describe exactly how many times
the memory element is repeated in order to clearly match the correct
instruction format.
For example,
vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to8} ; good
vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to16} ; fail qword * 16 = 1024b
vaddps zmm30,zmm29,DWORD [rcx]{1to16} ; good
vaddps zmm30,zmm29,DWORD [rcx]{1to8} ; fail dword * 8 = 256b
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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Giving a correct printf format specifier supresses the warning message.
And a local pointer variable is initialized with NULL.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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For instructions that can be encoded either in VEX or EVEX,
{evex} forces nasm to encode in EVEX.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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BND prefix is used for adding bounds checking protection
across flow control changes such as call, ret, jmp and jcc calls.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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Added MPX instructions and corresponding parser and encoder.
ICC style mib - base + disp and index are separate - is supported.
E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index
As a supplement to NASM style mib - split EA - parser,
omitted base+disp is now treated as 0 displacement.
E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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Mostly intended for the "mib" expressions in BNDLDX/BNDSTX.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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Factor out the parsing of an mref from parse_line(). In order to
support the [base,index] syntax we need to be able to parse an mref in
two steps.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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There is an awful lot of syntax-heavy "result->oprs[operand]" going
on; simplify by making a pointer to the current operand.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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Add the DZ and RESZ pseudoinstructions and add ZWORD to the
documentation.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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It was not so straight forward to find the postion of operand that has
a broadcasting, embedded rounding mode or SAE (Suppress All Exceptions)
decorator out from operands types or bytecode.
Remebering the postion of the operand of interest in the parser reduces
the burden that assembler looks through the operands.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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When a memory reference operand is a destination, this could have
an opmask decorator as well.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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ZWORD (512 bits) keyword is added
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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Previous comment was not so clear.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM),
opmask, broadcasting, embedded rounding mode,
suppress all exceptions, compressed displacement.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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AVX-512 introduced new syntax using braces for decorators.
Opmask, broadcat, rounding control use this new syntax.
http://software.intel.com/sites/default/files/319433-015.pdf
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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There are two instructions (VGATHERQPS, VPGATHERQD) where the only
separation between two forms is the vector length given to the vector
SIB. This means the *matcher* has to be able to distinguish
instructions by vector SIB length and the matcher only operates on the
operands and the instruction flags, not on the bytecode.
Export the vector index-ness into the operand flags and add to the
matcher.
This resolves BR 3392260.
Reported-by: Agner <agner@anger.org>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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We know that P_none = 0 thus instead of using
for() statement assign them all in one memset
call.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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It doesn't seem worth >200 lines of C and Perl to save ~50 lines in insns.dat.
In order to make this work I had to rename sbyte16/sbyte32 so that
they can take an ordinary size suffix (their size suffix was formerly
treated specially).
This fixes one disassembly bug: 48C7C000000080 disassembles to mov
rax,0x80000000, which reassembles to B800000080, which loads a
different value.
Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com>
Acked-by: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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Soon we will need to encode 512 bits values
thus there is no space left in our opflags_t
which is 32 bitfield.
Extend it to 64 bits width.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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This implements the mechanism for XACQUIRE/XRELEASE. It does not
include the necessary annotations in insns.dat.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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With HLE, the sequence REP LOCK actually makes sense, so support it.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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insn->prefixes might contain not only values from
'enum prefixes' but from 'enum reg_enum' as well so
make it generic 'int' instead.
This calms down the compiler about enum's mess and
eliminates a wrong assumption that we always have
values by particular type in this field.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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For big numbers it's easier to estimate bytes count
if they are written in hex notation. Let it be so.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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Handle immediate-size optimization for "mov r64,imm" -- reduce it to
"mov r32,imm32" or "mov r64,imm32" as appropriate.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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This reverts commit ac732cb6a599836bf4c988e59ac6de4498758c72.
Resolved Conflicts:
doc/nasmdoc.src
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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Two fixes:
1. Optimization of [bx+0xFFFF] etc
0xFFFF is an sbyte under 16-bit semantics,
so make sure to check it right.
2. Don't optimize displacements in -O0
Displacements that fit into an sbyte or
can be removed should *not* be optimized in -O0.
Implicit zero displacements are still optimized, e.g.:
[eax] -> 0 bit displacement, [ebp] -> 8 bit displacement.
However explicit displacements are not optimized:
[eax+0] -> 32 bit displacement, [ebp+0] -> 32 bit displacement.
Because #2 breaks compatibility with 0.98,
I introduced a new optimization level: -OL, legacy.
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optimization"
This reverts commit 41208028ff52d190044ee7532bf14c5aca0f899a.
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| From: "H. Peter Anvin" <hpa@zytor.com>
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| The tests for overflow_signed() are wrong too. Those are relevant for if a
| warning should be issued, but not for how the value should be encoded in
| the byte stream.
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Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
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No change on binary level
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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Instead of manipulating stdscan buffer pointer directly
we switch to a routine interface.
This allow us to unify stdscan access: ie caller should
"talk" to stdscan via stdscan_get/set routines.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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This allow us to eliminate code duplication
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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We should use overflow_ helpers before check if an immediate
operand fit a type range, otherwise we may loose high bits.
For example when we assemble the following instruction
imul eax,eax,0x10000
with -Ox passed we optimze it up to imm8 though it must be imm32.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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Consolidate I_none opcode to be used everywhere
instead of mix (-1,I_none).
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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Added a format attribute to nasm_error (only for GCC) and
used the resulting warnings to fix some format strings.
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We never invoked the parser with anything but the default definitions
for evaluate and efunc. Unlike the backend, though, we sometimes
invoke parse_line() with redefine_label() instead of define_label().
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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We never set ofmt and errfunc to anything but the global values.
Dropping them from the label definition function command line
simplifies the code.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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*To the best of my knowledge*, we now have authorization from everyone
who has significantly contributed to NASM in the past. As such,
change the license to the 2-clause BSD license.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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Add copyright headers to the *.c/*.h files in the main directory. For
files where I'm sure enough that we have all the approvals, I have
given them the 2-BSD license, the others have been given the "LGPL for
now" license header. Most of them can probably be changed after
auditing.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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Fix stray blank line in parser.c
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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OpenWatcom can't handle midcode variable declarations.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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A bracketed memory reference should be followed by a comma or
the end of the line. Enforce this.
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Also be optimistic with immediate forward references.
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WAIT is technically an instruction, but from an assembler standpoint
it behaves as if it had been a prefix. In particular, it has to be
ordered *before* any real hardware prefixes.
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